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Visitor c8yin
Visitor
435 Views
Registered: ‎09-17-2018

Constraining SGMII/GMII core in Device Specific Transceiver Configuration

I'm trying to use the 1G/2.5G Ethernet PCS/PMA or SGMII v16.1 Core with the VCU118 evaluation board to adapt the SGMII interface coming from the PHY to GMII for TEMAC. The core is customized to work as a GMII to SGMII bridge with the physical interface set to Device Specific Transceiver. I’ve incorporated the example design into my project, and am using constraints based on the datasheet for the VCU118 board. Namely:

 

set_property -dict {PACKAGE_PIN AU21 IOSTANDARD DIFF_HSTL_I_18} [get_ports txp]
set_property -dict {PACKAGE_PIN AV21 IOSTANDARD DIFF_HSTL_I_18} [get_ports txn]
set_property -dict {PACKAGE_PIN AU24 IOSTANDARD DIFF_HSTL_I_18} [get_ports rxp]
set_property -dict {PACKAGE_PIN AV24 IOSTANDARD DIFF_HSTL_I_18} [get_ports rxn]

where txp, txn, rxp, and rxn are the differential signals comprising the SGMII interface with the PHY. However, when I try to synthesize this design, I get the following error:

 

vado 12-1411] Cannot set LOC property of ports, Illegal to place instance gig_eth_pcs_pma_v16_1_example_design/core_support_i/pcs_pma_i/U0/transceiver_inst/gig_eth_pcs_pma_v16_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_eth_pcs_pma_v16_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST on site AU21. The location site type (HPIOB_M) and bel type (HPIOB_INBUF_M) do not match the cell type (GTYE4_CHANNEL). Instance gig_eth_pcs_pma_v16_1_example_design/core_support_i/pcs_pma_i/U0/transceiver_inst/gig_eth_pcs_pma_v16_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_eth_pcs_pma_v16_1_gt_gtwizard_gtye4_inst/gen_gtwizard_v4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST belongs to a shape with reference instance gig_eth_pcs_pma_v16_1_example_design/core_support_i/pcs_pma_i/U0/transceiver_inst/gig_eth_pcs_pma_v16_1_gt_i/inst/gen_gtwizard_gtye4_top.gig_eth_pcs_pma_v16_1_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape.

 

It seems like the core is looking for dedicated GT pins on the FPGA, but I’m constrained by the eval board design for the VCU118 and can’t change the pins that receive the SGMII signal from the PHY. Is there a way around this issue, or am I misunderstanding the error? Right now I'm looking into re-customizing the core to avoid needing an FPGA transceiver by using the Asynchronous SGMII over LVDS option, but the example design is only available as Verilog while the rest of my project is in VHDL, so I'd like to understand and act upon this error if possible. Appreciate any help, apologies in advance if I’m made any dumb errors (I’m pretty new to FPGAs).

 

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Moderator
Moderator
375 Views
Registered: ‎08-25-2009

Re: Constraining SGMII/GMII core in Device Specific Transceiver Configuration

Hi @c8yin,

 

In Vivado, you can use the board flow for Xilinx evaluation board to add the IP into your design; and the constraints will be setup automatically for you according to the board you select. Are you sure it matches the exact pins locations on VCU118? Can you check the board flow to confirm?

"Don't forget to reply, kudo and accept as solution."
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