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Visitor odergut
Visitor
7,095 Views
Registered: ‎06-23-2014

Customization of the 1000BASE‐X PCS/PMA Core v11.5

Hi there,

 

I have a question regarding the usage of the 1000BASE‐X PCS/PMA Core v11.5 (on a Kintex7 425T).

 

The example design provided with the core internally uses the Transceiver Wizard 2.5 to provide a transceiver bank. The user is invited to regenerate this part with the Transceiver Wizard to meet the personal requirements. The result is to be implanted back into the output of the PCS/PMA Core. I think, this is the way to go if -- for example -- one needs several network interfaces on a single bank, correct?

 

However, the Transceiver Wizard 2.5 might have some problems with the production silicon: The Answer Record 56454 [1] states, that version 2.6 contains fixes to support produciton silicon. Apparently, version 2.5 does not? Is it safe to use the Transceiver Wizard 2.5 to generate a transceiver bank to be used with the 1000BASE‐X PCS/PMA Core or is it necessary to upgrade to more recent version to ensure produciton silicon support?

 

Of course, it would also be possible to use a later version of the Transceiver Wizard, but the ports are quite different. This makes the substitution process much more cumbersome.

 

Thanks in advance for the help. Best,

 

Georg

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Xilinx Employee
Xilinx Employee
7,089 Views
Registered: ‎02-06-2013

Re: Customization of the 1000BASE‐X PCS/PMA Core v11.5

Hi

 

As the v11.5 core is production version you can target it directly and the port and attribute changes required for the production silicon will be already present with this core.

 

The general changes required to use multiple cores in the same quad in ISE are

 

We will need to keep a COMMON block in one of the core instantiations and remove the COMMON block from the rest of the core instantiations that use the same quad.

1) Generate two sets of cores with the same Ethernet core settings.

2) Leave the first set as is, but edit the second core set's GT instantiation (can be found in /<core_directory>/example_design/transceiver/<core_name>_gtwizard.v) so that it will not have GT#_COMMON blocks in them.

3) Replicate/Re-use the second core set as many times as needed and you will now be able to pack all the cores into a single quad.

 

But if you want to generate the transceiver wizard to customise the core then you need to use the latest version.

 

Also  there are few known issues which are not fixed with v11.5 that have to be taken care from the AR below and the corresponding workarounds present in the AR's.

http://www.xilinx.com/support/answers/47524.htm

 

 

If you can upgrade to Vivado there is a simple option of doing this by selecting the shared logic in core and shared logic in Example design option which will make targetting these cores in a single quad much easier without major changes required to be done.

 

You can find this in the latest PG047 document.

 

Regards,

Satish

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