01-07-2021 08:12 AM
I'm implementing an EtherCAT slave on ZedBoard and on Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit using the EtherCAT IP Core from Beckhoff GmbH. The interface between Ethenet PHY and EtherCAT IP Core is RGMII. RGMII uses double data rate (DDR). In the attached picture there are some DDR input and output cells, which are not the parts of the provided IP Core and must be implemented by the user. My question is, what exactly these DDR cells are and how I can implement them? There is no corresponding IP in the IP catalog from Xilinx in Vivado. I'm pretty new in FPGA programming and will be very grateful for the detailed explanation.
01-19-2021 09:29 AM
Hi @IvanDE ,
Where do you see this block diagram? Does EtherCAT user guide have more explanation? Xilinx does not provide EtherCAT IP core, I believe all info should be inside of the product guide of EtherCAT?
01-19-2021 10:11 AM - edited 01-19-2021 10:21 AM
It depends on the device family, e.g. IDDR/ODDR for 7 series, IDDRE1 (ISERDESE3)/ODDRE1 (OSERDESE3) for UltraScale.
I would expect that they could provide you an example.
You can also see what we did for our some of our RGMII interfaces here: https://www.xilinx.com/support/documentation/ip_documentation/tri_mode_ethernet_mac/v9_0/pg051-tri-mode-eth-mac.pdf
more details in the family user guides, e.g. for 7 series:
But there's also certainly some differences between 7 series HP vs 7 series HR, UltraScale HP vs HD, etc. in the I/O primitives and clocking approaches.
01-19-2021 12:50 PM
In the above post, links to related study materials are given. Just adding a bit more...
My question is, what exactly these DDR cells are and how I can implement them?
These are Xilinx primitives and you have to instantiate them in your RTL.
For an explanation of the IDDR/ODDR get the SelectIO Resources Guide for the Xilinx Zynq UltraScale+ (if it exists, sorry I am a Series7 FPGA guy).
For a template on how to instantiate the IDDR/ODDR get the Libraries Guide for the Xilinx Zynq UltraScale+ (if it exists, again sorry as I am a Series7 FPGA guy).
The docs for a 7 series FPGA are listed in the above post and I do not know if such a doc exists for Zynq UltraScale+ series.
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
01-19-2021 12:54 PM
Sorry - I missed the US+ (UltraScale+ reference).
Here are the corresponding docs for US/US+:
01-19-2021 01:23 PM
There are also primitive instantiation examples in Vivado, e.g.
tools -> language templates: VHDL -> Device Primitive Instantiation -> Kintex UltraScale+ -> Register -> DDR
ZU+ should be the same as KU+ here