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IvanDE
Newbie
Newbie
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Registered: ‎01-07-2021

DDR input/output cell

Hello,

I'm implementing an EtherCAT slave on ZedBoard and on Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit using the EtherCAT IP Core from Beckhoff GmbH. The interface between Ethenet PHY and EtherCAT IP Core is RGMII. RGMII uses double data rate (DDR). In the attached picture there are some DDR input and output cells, which are not the parts of the provided IP Core and must be implemented by the user. My question is, what exactly these DDR cells are and how I can implement them? There is no corresponding IP in the IP catalog from Xilinx in Vivado. I'm pretty new in FPGA programming and will be very grateful for the detailed explanation.

DDR_IO.png

Best regards

Ivan

DDR_IO.png
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nanz
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Registered: ‎08-25-2009

Hi @IvanDE ,

Where do you see this block diagram? Does EtherCAT user guide have more explanation? Xilinx does not provide EtherCAT IP core, I believe all info should be inside of the product guide of EtherCAT? 

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barriet
Xilinx Employee
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Registered: ‎08-13-2007

It depends on the device family, e.g. IDDR/ODDR for 7 series, IDDRE1 (ISERDESE3)/ODDRE1 (OSERDESE3) for UltraScale.

I would expect that they could provide you an example.

You can also see what we did for our some of our RGMII interfaces here: https://www.xilinx.com/support/documentation/ip_documentation/tri_mode_ethernet_mac/v9_0/pg051-tri-mode-eth-mac.pdf
or https://www.xilinx.com/support/documentation/ip_documentation/gmii_to_rgmii/v4_0/pg160-gmii-to-rgmii.pdf

 

more details in the family user guides, e.g. for 7 series:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug953-vivado-7series-libraries.pdf

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

But there's also certainly some differences between 7 series HP vs 7 series HR, UltraScale HP vs HD, etc. in the I/O primitives and clocking approaches.

Cheers,

bt

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barriet
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Registered: ‎08-13-2007

edit - minor correction above

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dpaul24
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Registered: ‎08-07-2014

@IvanDE ,

In the above post, links to related study materials are given. Just adding a bit more...

My question is, what exactly these DDR cells are and how I can implement them?

These are Xilinx primitives and you have to instantiate them in your RTL.

For an explanation of the IDDR/ODDR get the SelectIO Resources Guide for the Xilinx Zynq UltraScale+ (if it exists, sorry I am a Series7 FPGA guy).

For a template on how to instantiate the IDDR/ODDR get the Libraries Guide for the Xilinx Zynq UltraScale+ (if it exists, again sorry as I am a Series7 FPGA guy).

The docs for a 7 series FPGA are listed in the above post and I do not know if such a doc exists for Zynq UltraScale+ series.

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barriet
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Registered: ‎08-13-2007

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barriet
Xilinx Employee
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Registered: ‎08-13-2007

There are also primitive instantiation examples in Vivado, e.g.
tools -> language templates: VHDL -> Device Primitive Instantiation -> Kintex UltraScale+ -> Register -> DDR

ZU+ should be the same as KU+ here

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