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Adventurer
Adventurer
8,517 Views
Registered: ‎05-12-2014

DRC violation (PLHOLDVIO #1) in GTP example design

Hello,

 

I have encountered a DRC violation in the Artix 7 GTP example design that I cannot see how to work around. It is very easy to reproduce:

 

  1. Create a 7 Series FPGAs Transceivers Wizard IP using all default settings. It probably doesn't matter, but my target device is xc7a100tfgg484-1.
  2. Right-click on the IP and choose, "Open IP Example Design..."
  3. In the example design project, click "Run Synthesis."
  4. When synthesis is complete, open the synthesized design and click "Report DRC."
  5. Observe the "PLHOLDVIO #1" warning: "A LUT gtwizard_3_support_i/i_0 is driving clock pin of 218 cells. This could lead to large hold time violations. First few involved cells are..."

When I look at the synthesis schematic, it shows that a LUT1 has indeed been placed on the GT0_TXUSRCLK_OUT signal from the gt_usrclk_source block, although I can't see why this is the case by looking at the generated VHDL.

 

schematic.png

 

 

Any advice on how to remedy this DRC violation would be greatly appreciated. Thanks in advance!

 

Best regards,

Dave

 

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3 Replies
Community Manager
Community Manager
8,472 Views
Registered: ‎07-23-2012

Re: DRC violation (PLHOLDVIO #1) in GTP example design

Hi Dave,

 

I'm able to reproduce the error.

 

I see that the net that was driven by the LUT i_0 is gt0_txusrclk_i and it indeed drives 213 cells.

 

The attached screenshots confirm this.

 

Please provide me the .xci file to reproduce the issue at my end.

 

Regards,

Krishna 

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Adventurer
Adventurer
8,463 Views
Registered: ‎05-12-2014

Re: DRC violation (PLHOLDVIO #1) in GTP example design

Hi Krishna,

 

Thanks for looking into this. I have attached gtwizard_3.xci, which is the particular XCI file that I used when creating this post. I am getting the same DRC violation with other XCI configurations as well.

 

Please let me know if there is anything else I can do to help.

 

Thanks,

Dave

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Adventurer
Adventurer
8,447 Views
Registered: ‎05-12-2014

Re: DRC violation (PLHOLDVIO #1) in GTP example design

Hi Krishna,

 

I wanted to let you know I found that the violation can be fixed by removing the following attribute line from gtwizard_3_support.vhd:

 

attribute keep of gt0_txusrclk_i : signal is "true";