05-22-2014 01:01 PM
I have encountered a DRC violation in the Artix 7 GTP example design that I cannot see how to work around. It is very easy to reproduce:
When I look at the synthesis schematic, it shows that a LUT1 has indeed been placed on the GT0_TXUSRCLK_OUT signal from the gt_usrclk_source block, although I can't see why this is the case by looking at the generated VHDL.
Any advice on how to remedy this DRC violation would be greatly appreciated. Thanks in advance!
05-26-2014 03:30 AM
I'm able to reproduce the error.
I see that the net that was driven by the LUT i_0 is gt0_txusrclk_i and it indeed drives 213 cells.
The attached screenshots confirm this.
Please provide me the .xci file to reproduce the issue at my end.
05-27-2014 06:21 AM
05-30-2014 12:10 PM
I wanted to let you know I found that the violation can be fixed by removing the following attribute line from gtwizard_3_support.vhd:
attribute keep of gt0_txusrclk_i : signal is "true";