05-16-2014 12:03 PM
I am doing my final year project on displaying an image through the DVI port of the XUPV5LX110T virtex 5 fpga.
I programmed the CH7301C controller by its control registers and sent the data to be displayed. I have been working on it since months but nothing seems to be working.
With just a couple of days to go for the final submission, I request you to help with the code.
I wil be grateful if anyone sends me a code to display a picture.
I am attaching my code for any help that I can get.
Please help me at the earliest.
05-16-2014 12:33 PM
Your .rar file doesn't have the whole project in it. It's missing files from the My_IIC and DVI_Data directories. Looking at what source is actually in the archive doesn't show very much.
Can you describe what actual issues you're encountering? For example have you seen what looks like reasonable output in simulation, but you don't get a picture from the Chrontel device?
There are also quite a few other threads on the Chrontel circuit on your board in these forums. You might get some help just searching for Chrontel in the forums and see if any of those threads are helpful.
05-17-2014 11:41 AM
Thank you Gabor.
The thing is, I read the Chrontel controller datasheet and I got to know that I needed to configure the control registers in the controller for it to work. It could be done using IIC protocol. So I wrote my own IIC protocol and its tb waveform is working just fine.
Even the DVI_data module which has the data to be displayed is working in the simulation as I expected.
But there is no signal flowing out form the DVI port (shown as No Signal by the projector).
I am sending all 1's as the output so that I can get white colour.
I have attached the proper project files. Please review them again.
05-18-2014 07:07 PM
I only took a quick look at your I2C code, but it seems that it is too simplistic to work correctly. First your code is "ballistic" meaning that you set it off and it runs without regard to whether the I2C bus is actually accepting your commands. SDA and SCL are both bidirectional pins in a real I2C bus. For some applications, you can get away with a unidirectional SCL, but SDA must always be bidirectional even if you only do writes. That's because you need to check for acknowledge from the slaves. In addition, it looks like you're trying to run the I2C bus at 12.5 MHz (at least from the comments in your code) and most I2C slaves only run at 400 KHz max. There are also some indications that you don't really understand how synchronous logic works, for example using the same signal as a clock (scl_1) and as an input to the D of a flip-flop clocked by that signal:
. . .
scl_r = scl_1;
You might want to start by looking for a working I2C master design so you can at least get the Chrontel part initialized properly. Opencores.org has one, and there are probably others. I wrote my own, but I used the I2C bus specification and followed the rules for a multimaster-capable I2C bus running at 100 KHz.
Some points on I2C:
This is an open-drain (open-collector) bus. The circuit should only drive low or tristate on both SCL and SDA. It is not legal to drive high. Also, because the pullups are relatively weak compared to the capacitive bus load, you need to use feedback in your state machine to make sure that the line you have tristated actually went high before you move on to the next step in the sequence. This is especially true of the SCL line, where the slave is allowed to hold SCL low (clock stretching) if it can't keep up with the rate of the master.
The requirements are not too complex, but you need to be sure to respect all of the timing requirements in the specification. Any timing referencing the rising edge of a signal implies that you should start counting time after you have seen that signal rise, not from the time you tristated your driver. And you must look at the acknowledge signal from the slave to be sure that you are really communicating.