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Registered: ‎02-13-2013

Data integrity problem in V6HTX 10G PCS

Hi guys,


I am working on a project that use 10g ethernet on a V6 380HX. I followed the instruction on the 10g PCS user guide to duplicate the PCS and share the clocking resource among different ports of the GTH. Everything seems so great and I can get data from the TWO ports (yes I have a mac connected but that is not important).


Suddenly, I found that sometime one of the port will stop receiving data (tx on that port, and the tx/rx of the other port seems still fine). A closer look with chipscope showed that the XGMII signal I got from the error port is unstable, for example, I got something like D5_55_AB_11_55 .... in the permeable (which should be D5_55_55_55_55_55_55_55 ). The problem seems to be dependent on the image (i.e. sometimes it is fine, but sometimes it went wrong with just a little change in the entire source code). I double checked all the timing constraints and it seems that I haven't missed anything and timing clourse is met.


So my question is, what is the root cause of this problem. Is it because the GTH is not locked down properly? or is it because I have attached a chipscope analyzer which upset some of the timing constraints?


Any suggestions / comments are welcome. Thanks for your help : )



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