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Contributor
Contributor
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Registered: ‎07-03-2018

Device tree for 4 port Ethernet (10G/25G Ethernet subsystem) enable 1588 with RoE project

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Hi everybody,

 

I created design with roe_framer core (with 4 port Ethernet 10G setting) and then, run automation.

As everybody know, if we enable XILINX_AXI_EMAC_HWTSTAMP, we need assign axififo-connected and  xlnx,rxtsfifo like that:

axififo-connected = <&datapath_xxv_eth_subs_xxv_wrap_support_1588_2step_tx_ts_fifo_axi_fifo_mm_s_0>
xlnx,rxtsfifo = <&datapath_xxv_eth_subs_xxv_wrap_support_1588_2step_rx_ts_fifo_axi_fifo_mm_s_0>

That is for 1 port 10G Ethernet (such as port 1).

So how about 4 port? 

If we assign the same for port 2, port 3, port 4, errors could happen.

Error may be:

can't request region for resource [mem A009000 - A009FFFF]

with 0xA009000 is address of tx_ts_fifo above.

 

Does anyone have experienced about this problem, please help me to fix it.

 

Thank you,

Yurivn

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@yurivn 

Sorry for the late reply.

I have confirmed with our RoE team that the design only supports timestamping on port one. Further expansion is left to the user.

We have no plans to extend this at this time.

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@yurivn 

Can you let me know which example design you are working on?

Did you generate from block automation or the one download from GitHub?

Can you upload RoE xci file so I can know your settings?

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Contributor
Contributor
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Registered: ‎07-03-2018

@xud 

I generated from block automation.

The attached file is RoE xci file. You can check it.

Ps: I can't attach xci file, so I upload it to here:

 

Thank you, 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@yurivn 

Sorry for the late reply.

I have confirmed with our RoE team that the design only supports timestamping on port one. Further expansion is left to the user.

We have no plans to extend this at this time.

View solution in original post

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