07-21-2017 07:53 AM
please, can someone help me to build a design for 100 G Ethernet as in the figure below. I have a vcu108, I successfully generate 100 G using CMAC IP example design, but this example design send a limited number of packets and stop which is an issue for me. I need to generate a continuous flow of packets, that is why I need to build my own design.
Thank you in advance.
07-21-2017 08:53 AM
@elidrissi I am not familiar with this specific design but I am sure the Packet Generator has an option to control the quantity and type of packets created. Have you looked inside the implementation? Is that a hier or a Xilinx IP?
07-21-2017 09:02 AM
I didn't find any packet generator IP in Vivado. there is an axi_traffic_gen but its not compatible with cmac core.
07-21-2017 09:11 AM
@elidrissi So you are still building the design if I understand? I thought you had the example design.
If you actually get the design, open it and look inside, you might have a better view of what is needed.
07-21-2017 09:17 AM
yes I have the example design it work well, inside it there is a packet generator connected to the Lbus transmitter.
07-21-2017 09:18 AM
07-21-2017 12:30 PM