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Contributor
Contributor
2,998 Views
Registered: ‎11-08-2016

Diagram design for 100 G Ethernet using CMAC IP

Hi,

please, can someone help me to build a design for 100 G Ethernet as in the figure below. I have a vcu108, I successfully  generate 100 G using CMAC IP example design, but this example design send a limited number of packets and stop which is an issue for me. I need to generate a continuous flow of packets, that is why I need to build my own design.

Thank you in advance.

 

 

  100G.gif:

 

 Thank you.

 

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2,982 Views
Registered: ‎03-22-2016

Re: Diagram design for 100 G Ethernet using CMAC IP

@elidrissi  I am not familiar with this specific design but I am sure the Packet Generator has an option to control the quantity and type of packets created. Have you looked inside the implementation? Is that a hier or a Xilinx IP? 

 

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Contributor
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Registered: ‎11-08-2016

Re: Diagram design for 100 G Ethernet using CMAC IP

Hi,

I didn't find any packet generator IP in Vivado. there is an axi_traffic_gen but its not compatible with cmac core.

Thanks

 

 

.traffic_gen.gif

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Registered: ‎03-22-2016

Re: Diagram design for 100 G Ethernet using CMAC IP

@elidrissi So you are still building the design if I understand? I thought you had the example design.

If you actually get the design, open it and look inside, you might have a better view of what is needed.

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Registered: ‎11-08-2016

Re: Diagram design for 100 G Ethernet using CMAC IP

yes I have the example design it work well, inside it there is a packet generator connected to the Lbus transmitter. 

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Re: Diagram design for 100 G Ethernet using CMAC IP

@elidrissi So what is this packet generator? Is it a verilog module or a design hier block? 

 

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Re: Diagram design for 100 G Ethernet using CMAC IP

 it s a verilog module

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Re: Diagram design for 100 G Ethernet using CMAC IP

@elidrissi Can you look at what it is doing? Is there any counter? Can you share?

Or that's not the point? 

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