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Visitor syuan523
Visitor
19,431 Views
Registered: ‎09-18-2007

Dual Independent Aurora Links on One GTP Tile

Hi all,
Hope to get some guidance here.

Target device is the Virtex-5 LXT. I'm trying to build two independent Aurora links on one GTP tile. Independent meaning the two links will have to start/stop transmitting separate data streams individually. Data rate, clocks, resets, etc. can be the same.

I opened a webcase with Xilinx. But this is not one of the supported modes of operation of the GTP, they can not provide any guidance. The applicantion engineer told me that he heard about other customers that have done something similar, and he believes that they’ve got it working.

Any help will be appreciated,

Scott

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25 Replies
Xilinx Employee
Xilinx Employee
19,415 Views
Registered: ‎01-03-2008

Re: Dual Independent Aurora Links on One GTP Tile

While you can do this, providing that you use the same reference clock for each Aurora link, this is not a feature in the CoreGen Aurora LogiCore module and there are no plans to implement an enhancement to support this.

If you want to do this you will have to do this yourself.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Visitor syuan523
Visitor
19,360 Views
Registered: ‎09-18-2007

Re: Dual Independent Aurora Links on One GTP Tile

Just curious, is there a reason why this mode of operation is not supported?
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Xilinx Employee
Xilinx Employee
19,351 Views
Registered: ‎01-03-2008

Re: Dual Independent Aurora Links on One GTP Tile

It is a combination of a lack of demand, no one else had made request for this until your post that I am aware of, and available engineering resources.

Ed
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Newbie aleclair
Newbie
17,126 Views
Registered: ‎06-20-2008

Re: Dual Independent Aurora Links on One GTP Tile

I want to do the exact same thing with a V5 SX50T!  I have designed an entire architecure based on the fact that this should be flat out simple.  Has anyone gotten this to work?  Is it possible to send the same exact data out both Aurora links on one GTP tile?
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Xilinx Employee
Xilinx Employee
17,007 Views
Registered: ‎08-02-2007

Re: Dual Independent Aurora Links on One GTP Tile

1. Create two Aurora projects using CoreGen.

2. Combine them into one design.

 

This is what I can think about. But I haven't tried.

You may try it and if you meet any difficulty, you can post it. We can discuss.

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Newbie aleclair
Newbie
16,993 Views
Registered: ‎06-20-2008

Re: Dual Independent Aurora Links on One GTP Tile

Hi Scott,

 

I am checking with my local FAE to see if we can do what you want.  Perhaps my FAE will have a different path into the factory that will give us a better answer.  I already know that I can send identical data on two links from one Aurora core.

 

Aaron

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Contributor
Contributor
16,779 Views
Registered: ‎03-12-2008

Re: Dual Independent Aurora Links on One GTP Tile

It shouldn't be terribly difficult.  Mostly just alot of typing.

 

Just add the extra data and status ports to the top aurora module.

Then inside the top aurora module create a second instantiation of each lower level module, and connect to the previously unused half of the GTP.

 

I imagine that the biggest problem will be meeting timing, depending on the structure of the rest of your design.

 

It would be more difficult if you were looking for different data rates on the two Aurora channels.  Which could be accomplished, assuming that the data rates were multiples that the GTP internal PLL would support.

 

-Shawn

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14,673 Views
Registered: ‎10-13-2008

Re: Dual Independent Aurora Links on One GTP Tile

I needed this capability as well. The AVNET AES-XLX-V5SXT-PCIE95-G development board has two SFP interfaces which connect to a single GTP_DUAL instance. Each SFP connected to a fiber going to seperate destinations. Since the PCB wiring is fixed I was stuck trying to implement a solution using the existing Aurora code generated by coregen. While not logically difficult the janitorial engineering was error prone. It took me quite a while to get the two links up in simulation. Extracting the GTP_DUAL and bringing it up to the top level was not easy.

 

Based on the desire to support the AVNET card I would highly encourage Xilinx to support this capability in Coregen.

--
Aspen Logic, Inc.
http://aspenlogic.com
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Visitor lbeardsley1
Visitor
14,647 Views
Registered: ‎10-14-2008

Re: Dual Independent Aurora Links on One GTP Tile

My company has implemented this functionality.  It was painful and we incurred a lot of NRE to be able to accomplish it.  We have heard from our FAE that so many people are requesting that it will soon be part of the Architecture wizard.

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Observer ceedh4
Observer
12,080 Views
Registered: ‎06-03-2008

Re: Dual Independent Aurora Links on One GTP Tile

I wanted to do the same thing.

 

It was a bit tricky and a lot of typing but got it working without too much bother.

 

I've had it running on the ML506, 606, 607 boards.

 

Putting it into GoreGenerator would be really useful.

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Adventurer
Adventurer
12,043 Views
Registered: ‎01-28-2008

Re: Dual Independent Aurora Links on One GTP Tile

My design need this exact implementation, If coregen were to support this feature, it would really make my life a lot easier.

 

Regards,

 

Sanka

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Visitor noemartl3
Visitor
11,805 Views
Registered: ‎09-03-2008

Re: Dual Independent Aurora Links on One GTP Tile

I have the same need for my project. I have implemented what I think works. It is a little tricky. It will be nice if xilinx would support. By the way I opened a case and requested support and I got the same answer from the support.
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Contributor
Contributor
9,320 Views
Registered: ‎10-14-2008

So anybody did it since 2009???

So anybody did it since 2009???

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9,174 Views
Registered: ‎03-26-2011

Re: Dual Independent Aurora Links on One GTP Tile

Hi all,

 

This seems to have fallen off the radar but we're currently trying to implement this in a project on a Spartan-6 and thought I'd check again to see if anything has changed.  It doesn't seem to have made its way into the core gen, but maybe there's some new resource available?

 

Thanks!

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Moderator
Moderator
9,154 Views
Registered: ‎02-16-2010

Re: Dual Independent Aurora Links on One GTP Tile

Have you checked Appendix A in Aurora user guide
http://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b_ug353.pdf
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Newbie fpgazealot
Newbie
9,054 Views
Registered: ‎04-03-2012

Re: Dual Independent Aurora Links on One GTP Tile

Did anyone accomplish this ?

Can someone post some vhdl or verilog source on how to accomplish this ?

It is not possible with the latest and greatest tools, it simply does not allow you to place the pads.

Pls advise

tx

 

Tags (1)
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Newbie fpgazealot
Newbie
9,053 Views
Registered: ‎04-03-2012

Re: Dual Independent Aurora Links on One GTP Tile

Hi,

 

This does not help at all.

Page 113 onwards  is not even in-line with the latest reference design (Spartan-6)

One would expect better from a company like Xilinx.

 

Please show how to do it in VHDL.

 

FZ

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Newbie fpgazealot
Newbie
9,052 Views
Registered: ‎04-03-2012

Re: Dual Independent Aurora Links on One GTP Tile

@Kurtis,

 

Were you able to do it on the Spartan-6 ?

Could you show how ?

FZ

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9,005 Views
Registered: ‎06-09-2012

Re: Dual Independent Aurora Links on One GTP Tile

Hi,I needed this capability as well.Target device is the Virtex-5 SX95T. But I'm trying to build two simplex Aurora links on one GTP tile.One Aurora  is composed of  two TX ,and another is composed of two RX in the same GTP tile. If it is

possible ,how can I do this?

 

Thank you.

Tags (1)
0 Kudos
6,253 Views
Registered: ‎03-26-2011

Re: Dual Independent Aurora Links on One GTP Tile

Although we decided to forgo this functionality for a while since it wasn't strictly necessary at the time, I can confirm that this does now work with a Spartan 6 LX150T.

 

I was successful with ISE 13.2, ipcore Aurora 8B10B v6.2.  I followed the brief instructions in the v5.2 user guide, Appendix A, which seemed equally applicable for v6.2.  The instructions are a bit sparse, but overall it's not too complicated.  It took a few hours of carefully renaming/mapping/remapping signals.  Here's an outline of changes I made to the example design:

 

<design_name>_tile.vhd :

No changes required

 

<design_name>_transceiver_wrapper.vhd :

I essentially changed every port to include a subscript for transceiver 0 or 1.  For example,

 

LOOPBACK_IN becomes two ports: LOOPBACK_IN_0 and LOOPBACK_IN_1

 

The only ports that are NOT duplicated in this way are:

 

ENCHANSYNC_IN, CHBONDDONE_OUT, CHBONDDONE_OUT_unused, REFCLK, GTPRESET_IN

 

In fact, I believe the first three in this list can be left out entirely.  At least in the case of my application, these are not used at all, since I'm only using one lane per channel.  These new ports have to be mapped appropriately to the GTP tile.  I believe this is fairly self explanatory.  PLLLKDET_OUT_0 and PLLLKDET_OUT_1 have to be mapped manually, since they connect to the tile via an internal signal.

 

<design_name>.vhd :

 

The changes here are more involved.  Again, all the ports need to be duplicated for the 0 and 1 transceivers.  For example, DO_CC becomes DO_CC_0 and DO_CC_1.  The following ports do NOT need to be duplicated:

 

GTPD2, RESET, GT_RESET

 

In the list of signal declarations, many signals should be changed to reflect that one will be used for one transceiver and the other for the other transceiver.  There are too many to list here.

 

You will need two instantiations of each of the following:

 

<design_name>_AURORA_LANE_4BYTE

<design_name>_GLOBAL_LOGIC

<design_name>_AXI_TO_LL

<design_name>_TX_STREAM

<design_name>_LL_TO_AXI

<design_name>_RX_STREAM

 

 

And only one instantiation of:

 

<design_name>_GTP_WRAPPER

 

Look at the signal connections here carefully to see what should be duplicated for the second lane.

 

<design_name>_example_design.vhd :

 

The changes here are similar to those in <design_name>.vhd.  I ended up duplicating the following components:

 

BUFIO2 (for gtpclkout_i)

<design_name>_CLOCK_MODULE

<design_name>_AXI_TO_LL

<design_name>_FRAME_CHECK

<design_name>_LL_TO_AXI

<design_name>_FRAME_GEN

 

The following components only have 1 instance:

 

IBUFDS (for GTPD2_P/N)

<design_name>.vhd

 

Some of the wiring needs to be duplicated as well.  And of course, all the new connections need to be made to the duplicated blocks.

 

Hopefully this helps others who might be trying to do the same thing.

 

-K

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6,238 Views
Registered: ‎03-26-2011

Re: Dual Independent Aurora Links on One GTP Tile

There's one thing that's still not entirely cleat to me, which is whether I can use the same USER_CLK for both links or whether they must be independent. I can say that it works with separate clocks, but I would rather combine them to save clocking resources.

Does anyone know offhand?
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Scholar samcossais
Scholar
5,996 Views
Registered: ‎12-07-2009

Re: Dual Independent Aurora Links on One GTP Tile

I wish this functionality was implemented actually.

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Scholar samcossais
Scholar
5,955 Views
Registered: ‎12-07-2009

Re: Dual Independent Aurora Links on One GTP Tile


@kurtis.nishimura wrote:
There's one thing that's still not entirely cleat to me, which is whether I can use the same USER_CLK for both links or whether they must be independent. I can say that it works with separate clocks, but I would rather combine them to save clocking resources.

Does anyone know offhand?

Yes you can combine them. Even with other protocol using the same reference clock, as long as you are careful with their respective initialization process.

 

I think in many of the Xilinx IPs, there is a clocking module included that could actually be shared with other modules, so that you can share the clock to avoid additional clock ressources AND additional logic/memory for clock domain crossing. I just wish these IP clocking modules could be user defined.

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5,361 Views
Registered: ‎11-03-2013

Re: Dual Independent Aurora Links on One GTP Tile

Hey friend, I wanted the same requirement and did this successfully. If you want the project just mail me I will send you. We have to duplicate the signals, but you have to select only one lane out of that dual tile during the lane selection in the GUI.
jeevanreddymandali@gmail.com
jeevanreddymandali
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5,360 Views
Registered: ‎11-03-2013

Re: So anybody did it since 2009???

Hey friend, I wanted the same requirement and did this successfully. If you want the project just mail me I will send you. We have to duplicate the signals, but you have to select only one lane out of that dual tile during the lane selection in the GUI.
jeevanreddymandali@gmail.com
jeevanreddymandali
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