03-25-2008 11:33 AM
Hope to get some guidance here.
Target device is the Virtex-5 LXT. I'm trying to build two independent
I opened a webcase with Xilinx. But this is not one of the
supported modes of operation of the GTP, they can not provide any guidance. The applicantion engineer told me that he heard about other customers
that have done something similar, and he believes that they’ve got it working.
Any help will be appreciated,
03-25-2008 06:06 PM
04-15-2008 01:38 PM
06-20-2008 04:12 PM
06-24-2008 12:36 AM
1. Create two Aurora projects using CoreGen.
2. Combine them into one design.
This is what I can think about. But I haven't tried.
You may try it and if you meet any difficulty, you can post it. We can discuss.
06-24-2008 08:36 AM
I am checking with my local FAE to see if we can do what you want. Perhaps my FAE will have a different path into the factory that will give us a better answer. I already know that I can send identical data on two links from one Aurora core.
07-01-2008 02:42 PM
It shouldn't be terribly difficult. Mostly just alot of typing.
Just add the extra data and status ports to the top aurora module.
Then inside the top aurora module create a second instantiation of each lower level module, and connect to the previously unused half of the GTP.
I imagine that the biggest problem will be meeting timing, depending on the structure of the rest of your design.
It would be more difficult if you were looking for different data rates on the two Aurora channels. Which could be accomplished, assuming that the data rates were multiples that the GTP internal PLL would support.
10-13-2008 12:46 PM
I needed this capability as well. The AVNET AES-XLX-V5SXT-PCIE95-G development board has two SFP interfaces which connect to a single GTP_DUAL instance. Each SFP connected to a fiber going to seperate destinations. Since the PCB wiring is fixed I was stuck trying to implement a solution using the existing Aurora code generated by coregen. While not logically difficult the janitorial engineering was error prone. It took me quite a while to get the two links up in simulation. Extracting the GTP_DUAL and bringing it up to the top level was not easy.
Based on the desire to support the AVNET card I would highly encourage Xilinx to support this capability in Coregen.
10-14-2008 11:00 AM
My company has implemented this functionality. It was painful and we incurred a lot of NRE to be able to accomplish it. We have heard from our FAE that so many people are requesting that it will soon be part of the Architecture wizard.
11-24-2008 04:08 AM
I wanted to do the same thing.
It was a bit tricky and a lot of typing but got it working without too much bother.
I've had it running on the ML506, 606, 607 boards.
Putting it into GoreGenerator would be really useful.
12-01-2008 03:42 AM
My design need this exact implementation, If coregen were to support this feature, it would really make my life a lot easier.
01-12-2009 05:26 PM
05-27-2011 03:19 PM
This seems to have fallen off the radar but we're currently trying to implement this in a project on a Spartan-6 and thought I'd check again to see if anything has changed. It doesn't seem to have made its way into the core gen, but maybe there's some new resource available?
05-30-2011 07:52 PM
04-03-2012 05:30 AM
Did anyone accomplish this ?
Can someone post some vhdl or verilog source on how to accomplish this ?
It is not possible with the latest and greatest tools, it simply does not allow you to place the pads.
04-03-2012 05:35 AM
This does not help at all.
Page 113 onwards is not even in-line with the latest reference design (Spartan-6)
One would expect better from a company like Xilinx.
Please show how to do it in VHDL.
06-09-2012 07:38 PM
Hi,I needed this capability as well.Target device is the Virtex-5 SX95T. But I'm trying to build two simplex Aurora links on one GTP tile.One Aurora is composed of two TX ,and another is composed of two RX in the same GTP tile. If it is
possible ,how can I do this?
09-17-2012 05:21 PM
Although we decided to forgo this functionality for a while since it wasn't strictly necessary at the time, I can confirm that this does now work with a Spartan 6 LX150T.
I was successful with ISE 13.2, ipcore Aurora 8B10B v6.2. I followed the brief instructions in the v5.2 user guide, Appendix A, which seemed equally applicable for v6.2. The instructions are a bit sparse, but overall it's not too complicated. It took a few hours of carefully renaming/mapping/remapping signals. Here's an outline of changes I made to the example design:
No changes required
I essentially changed every port to include a subscript for transceiver 0 or 1. For example,
LOOPBACK_IN becomes two ports: LOOPBACK_IN_0 and LOOPBACK_IN_1
The only ports that are NOT duplicated in this way are:
ENCHANSYNC_IN, CHBONDDONE_OUT, CHBONDDONE_OUT_unused, REFCLK, GTPRESET_IN
In fact, I believe the first three in this list can be left out entirely. At least in the case of my application, these are not used at all, since I'm only using one lane per channel. These new ports have to be mapped appropriately to the GTP tile. I believe this is fairly self explanatory. PLLLKDET_OUT_0 and PLLLKDET_OUT_1 have to be mapped manually, since they connect to the tile via an internal signal.
The changes here are more involved. Again, all the ports need to be duplicated for the 0 and 1 transceivers. For example, DO_CC becomes DO_CC_0 and DO_CC_1. The following ports do NOT need to be duplicated:
GTPD2, RESET, GT_RESET
In the list of signal declarations, many signals should be changed to reflect that one will be used for one transceiver and the other for the other transceiver. There are too many to list here.
You will need two instantiations of each of the following:
And only one instantiation of:
Look at the signal connections here carefully to see what should be duplicated for the second lane.
The changes here are similar to those in <design_name>.vhd. I ended up duplicating the following components:
BUFIO2 (for gtpclkout_i)
The following components only have 1 instance:
IBUFDS (for GTPD2_P/N)
Some of the wiring needs to be duplicated as well. And of course, all the new connections need to be made to the duplicated blocks.
Hopefully this helps others who might be trying to do the same thing.
09-18-2012 08:10 PM
11-21-2012 12:57 AM
There's one thing that's still not entirely cleat to me, which is whether I can use the same USER_CLK for both links or whether they must be independent. I can say that it works with separate clocks, but I would rather combine them to save clocking resources.
Does anyone know offhand?
Yes you can combine them. Even with other protocol using the same reference clock, as long as you are careful with their respective initialization process.
I think in many of the Xilinx IPs, there is a clocking module included that could actually be shared with other modules, so that you can share the clock to avoid additional clock ressources AND additional logic/memory for clock domain crossing. I just wish these IP clocking modules could be user defined.
02-25-2014 10:20 PM
02-25-2014 10:21 PM