12-29-2015 10:49 PM
I am using AEL 2005 PHY in HTG-FMC-SFP-PLUS card that is further interfaced with FPGA (10 G XAUI and MAC core design).
When i test all the internal loopback (PMA,PCS, or PHY) it works better. But when i use external loop back via EDC connection breaks exact after 4 minutes and data transmission between SFPs got stuck.
Any suggestions please
12-30-2015 11:12 PM
05-07-2018 06:17 AM - edited 05-07-2018 06:19 AM
07-20-2019 02:53 PM
I have same issue. core status signals are 8'b1111_1100 during design stuck off. when i reset phy manual and reconfigure phy, then design starts for nearly about 5 minutes. Plz tell me on forum or in box me at firstname.lastname@example.org.