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Visitor
Visitor
6,514 Views
Registered: ‎12-09-2015

EDC issue

Dear All,

I am using AEL 2005 PHY in HTG-FMC-SFP-PLUS card that is further interfaced with FPGA (10 G XAUI and MAC core design).

When i test all the internal loopback (PMA,PCS, or PHY) it works better. But when i use external loop back via EDC connection breaks  exact after 4 minutes and data transmission between SFPs got stuck.

Any suggestions please

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Moderator
Moderator
6,410 Views
Registered: ‎02-16-2010

What is EDC? What is the role of the EDC?

Please provide the core status details during the failure.
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Visitor
Visitor
1,092 Views
Registered: ‎12-11-2017

How did you resolve the issue? I encountered the same issue on the same platform (HTG-FMC-SFP-PLUS).

I did the internal loopback perfectly. However, when performing external loopback with twinax cable, the communication was stuck after five minutes.

 

Please help me

 

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Contributor
Contributor
400 Views
Registered: ‎11-04-2014

I have also same issue. Plz tell me about this issue if anyone have resolved this issue.

 

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Contributor
Contributor
324 Views
Registered: ‎11-04-2014

Hi all 

I have same issue. core status signals are 8'b1111_1100 during design stuck off. when i reset phy manual and reconfigure phy, then design starts for nearly about 5 minutes. Plz tell me on forum or in box me at latif_kcp@hotmail.com.

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