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Registered: ‎04-20-2011

Elastic Buffer with clock correction in User Logic?

Hi community,


is there a possibility to use the Elastic Buffer with Clock Correction which is implemented in the GTX Transceivers in Virtex-6 user logic?

I would like to receive 1000Base-X Ethernet Data with one clock and send it with another. Both are 100ppm around 125Mhz but they are different. So Frames would be dropped if I'd try this without clock correction.

I wanted to program it with the help of FiFo Generator. But I have no Idea how I should do the clock correction with it. There are inputs for the read and the write clock but my Idea to do a clock correction was giving a read and a write pointer to it, so I can just shift the pointer if 'm doing the correction (adding or leaving Idles).

I have also found the elastic_buffer file of the 1000Base-X core, but I need to do the clock correction at 10B.

Is there an easier way do implement a fifo or elastic buffer with clock correction?


I hope you can help me...


Thanks a lot in advance!

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2 Replies
Registered: ‎11-06-2019

Have you solved the problem? I have faced similar problem with GTY transceiver, for 10GBASE-R

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Registered: ‎08-25-2009

HI @upside_down ,

Can you please post your question with starting a new thread on forum? The post that you are following up is from 2012 which is quite old. A new post is much more likely to be answered by our ethernet experts and community members. Thank you!



"Don't forget to reply, kudo and accept as solution."
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