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Adventurer
Adventurer
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Registered: ‎05-18-2018

Enabling TSU for PL use only in the Ultrascale+

I am using the Ultrascale+ and Vivado 2019.1.

I am trying to enable the 1588 time stamp unit (TSU) in the fabric.

Per AR 67239, I enabled GEM 0. In screen ZynqUS+ re-customize>I/O Configuration>High Speed, I have GEM 0 I/O set to EMIO. The drop-down options 'GT Lane 0' and 'MIO 26 ... 37' are not valid and show red. (They are both being used elsewhere in the design.)

gem_peripheral_setup.png

 

In screen ZynqUS+ re-customize>Clock Configuration>Output Clocks, Gem 0 is driven by an IOPLL at 125 MHz nominal, and GEM_TSU is driven by an IOPLL at 250 MHz nominal.

According to the PDF in AR 67239, "When you enable GEM ... but without selecting the GEM TSU Clock, it will use the 250 MHz PS internal IOPLL as the GEM TSU clock by default." Since I have not checked the External TSU Clock box, I am assuming that the TSU is being clocked internally at 250 MHz.

gem_clocks.png

 

These settings expose emio_enet0_enet_tsu_timer_cnt[93:0] on the Zynq block. I am feeding this 94-bit vector to a slice IP block to grab bits emio_enet0_enet_tsu_timer_cnt[53:46] and send them to an AXI slave.

Despite what the PDF says on page 3, signals fmio_gem0_tsu_clk_to_pl_bufg and fmio_gem0_tsu_clk_to_pl_bufg are NOT exposed.

gem_zynq_block_w_destination.png

 

Questions:

 - No data is appearing on emio_enet0_enet_tsu_timer_cnt[93:0]. Any idea why?

 - Can this be enabled by configuring only the PL (no firmware/PS settings changes)?

 - Must fmio_gem0_tsu_clk_to_pl_bufg drive fmio_gem0_tsu_clk_to_pl_bufg, and must I manually tie them together? If they are only brought out when I select External TSU Clock, but the MIO 50, 51 for driving this signal are already used, am I going to have to do a hardware change in order to use the TSU?

 

 

 

gem_clocks.png
gem_peripheral_setup.png
gem_zynq_block_w_destination.png
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3 Replies
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Moderator
Moderator
285 Views
Registered: ‎08-25-2009

Re: Enabling TSU for PL use only in the Ultrascale+

Hi @joelschad ,

How did you check the value on this port? Do you have an SW application that does timestamping frames?

In the later version of the tool, signals fmio_gem0_tsu_clk_to_pl_bufg and fmio_gem0_tsu_clk_to_pl_bufg are connected internally by default for customers. So you do not need to worry about this connection. And it's not necessary to have an extenral TSU clock on your board to make TSU work.

 

"Don't forget to reply, kudo and accept as solution."
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Adventurer
Adventurer
273 Views
Registered: ‎05-18-2018

Re: Enabling TSU for PL use only in the Ultrascale+

I have not been able to get the TSU working so far.

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Moderator
Moderator
259 Views
Registered: ‎08-25-2009

Re: Enabling TSU for PL use only in the Ultrascale+

Hi @joelschad ,

Please provide more details on the failure. Regardless of this port, have you checked the TSU relavent registers and see if the values there are correct?

 

"Don't forget to reply, kudo and accept as solution."
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