cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
xilinxuser1
Visitor
Visitor
306 Views
Registered: ‎07-30-2020

Ethernet 10g AXI Interface - Simulation Errors

Hello,

I have generated a 10g Ethernet core with AXI interface, and have found that during a simulation, internal Ethernet register read commands will return an 'X' (undefined). Reading the following registers will return an 'X':

STAT_RX_TOTAL_PACKETS_MSB (080C)

STAT_RX_TOTAL_PACKETS_LSB (0808)

STAT_RX_TOTAL_GOOD_PACKETS_MSB (

I am sure if I tried other registers I would get similar results.

I am using the following tool settings:

Xilinx UltraScale+ Zynq

Vivado 2019.1

Cadence Xcelium 20.03.005

Is there anything specifically that needs to be done to properly read Ethernet core registers using AXI interface?

Thanks,

Tony

0 Kudos
3 Replies
nanz
Moderator
Moderator
299 Views
Registered: ‎08-25-2009

Hi @xilinxuser1 ,

In your simulation, you see a successful linkup and packet transactions? Have you tried the example design simulation directly? Or in Vivado/Questa simulator to see if that works well? 

I'd recommend starting with example design simulation and checking the waveform to compare the sequences. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
0 Kudos
xilinxuser1
Visitor
Visitor
238 Views
Registered: ‎07-30-2020

Yes, I can see successful packet transactions, only reading of the AXI interface registers shows undefined data. 

I have tried the example design, and it was able to run correctly, but I do not recall seeing multiple AXI interface register read transactions. It would be ideal to have the example design run ethernet packets through the core, and read several ethernet registers, similar to ones I have listed in the original post.

0 Kudos
nanz
Moderator
Moderator
228 Views
Registered: ‎08-25-2009

Hi @xilinxuser1 ,

Can you please upload your simulation waveform so I could take a look? Thank you!


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
0 Kudos