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Registered: ‎10-17-2019

Ethernet AXI 1G/2.5G Ethernet Subsystem 7.1

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Hello,

I want to implement ethernet functionality using "AXI 1G/2.5G Ethernet Subsystem 7.1" IP on xc7z035ifbg676-2L (active) device.

I have created example design and then trying to implement it to write constraints :

# ethernet-1 (U1,B20,PS_MIO51_501_JX4,JX4,100,ETH1_RESETN)

set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports eth1_mdc] ; ## U1,B10,IO_L16_34_JX4_P,JX4,58,ETH1_MDC
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports eth1_mdio] ; ## U1,A10,IO_L16_34_JX4_N,JX4,60,ETH1_MDIO
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxclk] ; ## U1,G7,IO_L12_MRCC_34_JX4_P,JX4,46,ETH1_RX_CLK
set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxctl] ; ## U1,F7,IO_L12_MRCC_34_JX4_N,JX4,48,ETH1_RX_CTRL
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[0]] ; ## U1,E6,IO_L10_34_JX4_P,JX4,42,ETH1_RXD0
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[1]] ; ## U1,D5,IO_L10_34_JX4_N,JX4,44,ETH1_RXD1
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[2]] ; ## U1,F8,IO_L11_SRCC_34_JX4_P,JX4,45,ETH1_RXD2
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[3]] ; ## U1,E7,IO_L11_SRCC_34_JX4_N,JX4,47,ETH1_RXD3
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txclk] ; ## U1,C8,IO_L13_MRCC_34_JX4_P,JX4,51,ETH1_TX_CLK
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txctl] ; ## U1,C7,IO_L13_MRCC_34_JX4_N,JX4,53,ETH1_TX_CTRL
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[0]] ; ## U1,D6,IO_L14_SRCC_34_JX4_P,JX4,52,ETH1_TXD0
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[1]] ; ## U1,C6,IO_L14_SRCC_34_JX4_N,JX4,54,ETH1_TXD1
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[2]] ; ## U1,C9,IO_L15_34_JX4_P,JX4,57,ETH1_TXD2
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[3]] ; ## U1,B9,IO_L15_34_JX4_N,JX4,59,ETH1_TXD3

# clocks

create_clock -period 8.000 -name eth1_rgmii_rxclk [get_ports eth1_rgmii_rxclk]

 

set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_0_p] ; ## U1,R6,UNNAMED_7_CAP_I123_N2,JX1,87,MGTREFCLK0_112_JX1_P
set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_0_n] ; ## U1,R5,UNNAMED_7_CAP_I125_N2,JX1,89,MGTREFCLK0_112_JX1_N

## clocks
create_clock -name ref_clk -period 5.00 [get_ports gt_ref_clk_0_p]

 

I am not getting the clock :

facing:

WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ILA' at location 'uuid_7C6A6FE445255A57804F5689CD836BF4' from probes file, since it cannot be found on the programmed device.

 

What i missed here...I am attaching design flow

Tags (2)
Design_Flow_Ethernet.png
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1 Solution

Accepted Solutions
nanz
Moderator
Moderator
284 Views
Registered: ‎08-25-2009

Hi kumar090192@gmail.com ,

Your latest question seems to be related to programming IC clock with SPI. This is not related to Ethernet so I have moved your new post to a different forum board to get some help. For this one, you can either close it by marking the accepted solution first until you get a solution for SPI programming and you can repost your ethernet issue here. 

I believe most likely it's due to you do not have a valid GT clock. 


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If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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6 Replies
nanz
Moderator
Moderator
501 Views
Registered: ‎08-25-2009

Hi kumar090192@gmail.com ,

It seems it's the debug hub core does not have the clock. When you add ILA core in the design, you should assign associated clock to the signals you need to capture. How did you add the debug core into the design?


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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488 Views
Registered: ‎10-17-2019

Hello i have assigned gt clock only to ILA <"gt_ref_clk_0_p" ,"gt_ref_clk_0_n">

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dpaul24
Scholar
Scholar
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Registered: ‎08-07-2014

kumar090192@gmail.com ,

It seems either you have not added the ILA core to your project or if added and instantiated, the ILA clock might not be connected. This is what I feel from those warning messages.

Can you should us HOW, 1) the ILA core is added to your project, and 2) the instantiation of the ILA core with the signals connected?

------------FPGA enthusiast------------
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471 Views
Registered: ‎10-17-2019

clock i have assigned is GT clock only..i think GT clock is not coming. Is there any process have to do to get gt clock ?

 

ILA:ILA_1
PORT MAP(

CLK => gt_clk,

PROBE0 => o_m_axis_rxd_tdata,
PROBE1 => o_m_axis_rxd_tvalid

);

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375 Views
Registered: ‎10-17-2019

I have seen this GT clock is coming fromAD9517-3 clock generator. And there is a serial SPI interface. So shall I need to program this clock generator? And if yes the can i get this SPI verilog /VHDl code some where?

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nanz
Moderator
Moderator
285 Views
Registered: ‎08-25-2009

Hi kumar090192@gmail.com ,

Your latest question seems to be related to programming IC clock with SPI. This is not related to Ethernet so I have moved your new post to a different forum board to get some help. For this one, you can either close it by marking the accepted solution first until you get a solution for SPI programming and you can repost your ethernet issue here. 

I believe most likely it's due to you do not have a valid GT clock. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post

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