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Registered: ‎12-11-2014

Ethernet PCS/PMA or SGMII IP V15.1 Remote Fault Problem

Hello All,

I am trying to implement AXI Ethernet Subsystem (v7.0 Rev2) on KCU105 board using Vivado 2015.3.

As you may know, AXI Ethernet Subsystem contains 3 sub IPs which are Tri Mode Ethernet MAC V9.0 (Rev2), 1G/2.5G Ethernet PCS/PMA or SGMII (V15.1) and Utility Vector Logic (V2.0 Rev1).

 I have generated the IP using the settings that are given in the attached file.

As it is given in the document the IP works in SGMII on LVDS mode.


I use AXI Ethernet Subsystem example design that provided by Vivado tool as a reference.

I only removed the loopback from the example design. .  

The design works fine with two channel data processing block which is a custom logic.

Bu If I increase the number of channel processing block by instantiating 12 of them than Ethernet IP does not work properly anymore. Link between on board PHY (Marwell Alaska) and PC seems working since I see the Ethernet link status LED is on. When I check Local Area Connection Status on PC I also see link speed is set to 1000mbps as expected.

But When I check the status vector [13:8] of Ethernet PCS/PMA or SGMII IP, I see it is 6’b111000.

The 13th bit is high and it means there is a “remote fault but I could not point out the problem so far.

The status vector [13:8] of Ethernet PCS/PMA or SGMII IP is 6’b011000 in the working design.


AXI lite controller follows the following configuration steps after reset;

  • SET MDIO frequency; 0x68 value is written to the MDIO configuration register on the TEMAC
  • Set external PHY REG 0 : 0x1140 value is written to control register of the external PHY
  • Set Internal PHY REG 0 : 0x1140 value is written to control register of the internal PHY (PCS/PMA or SGMII)
  • Reset receiver: 0x10000000 value is written to TEMAC Receiv Configuration Word 1 (0x404) register.
  • Reset transmitter: 0x10000000 value is written to TEMAC Transmit Configuration Word 1 (0x408) register.
  • Disable flow control: 0x00000000 value is written to Flow Control Configuration (0x40C) register
  • Set filter masking index register : 0x00000000 value is written to TEMAC Address Filter Mask Index (0x708) register
  • Set configuration address filter 1 register :
  • Set configuration address filter 2 register :
  • Go to last state.


A missing constraint could be a problem but I use all the constraint that are provide by IP.

Still I could not solve the issue, all your comments and suggestions are welcome.

Thanks in advanced.



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Xilinx Employee
Xilinx Employee
Registered: ‎02-06-2013



How are you generation and driving the driving the LVDS reference clock.


It should be synchronous and you should use the 625Mhz clock provided by the PHY.


Vivado 2015.4 has this option corrected taking 625Mhz instead of 125Mhz as shown from your settings for the SGMII IP.


Can you try with 2015.4 and let us know the status.



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Registered: ‎12-11-2014

Dear Satish,


I have generated AXI Ethernet Subsystem as "Block Design"  thus "1G/2.5G Ethernet PCS/PMA or SGMII" IP is added automatically to BD. I cannot change the referece clock frequency of LVDS though AXI Ethernet IP settings. There is option to change it.   It is set 125MHz by Vivado automatically. Where is the option that you mentioned to correct reference clock?


I have re-generated the AXI Ethernet Subsystem IP using Vivodo 2015.4 as you sugessted but still LVDS reference clock is  125MHz and I could NOT find the option to change it.



Kind regards,



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