02-05-2017 10:15 AM - edited 02-15-2017 11:47 AM
I currently use XC7Z045 SoC . and I have another SoC XC7Z020. There is an LVDS Sgmii line betweem them. I try to communicate two SoC over sgmii line.
1 . When XC7Z045 is in cascaded jtag mode, I can debug my Software using ARM DS-5 emulator connected to dedicated pins in PL JTAG side. I use Ethernet that is connected to ENET0 of XC7Z045 over a PHY to read / write some register values or send commands from my desktop application software. ENET1 is connected to sgmii ip.
2. When XC7Z045 changed to independent jtag mode, ( now ARM DS-5 is connected to PJTAG MIO side for debub) PHY_Adress_Read_Error such an error returns. I looked at in debug mode when PHY driver running. There is a PHY adress finding or reading loop. ın cascaded mode, as above explained, correct PHY adress found, that is 1. As hard Coded in PHY. But when changing jtag mode into independent, PHY adress finding loop can not find the correct adress. That loop searches the a PHY adress from 1 to 32.
I use the below same project for above 2 case. Zynq processing system + sgmii ip.
3. For trying, I put only Zynq processing system opened ENET0, When XC7Z045 changed to independent jtag mode. PHY address could be found correclty as 1.
So, the problem, when I open the second ENET1 to connect sgmii ip, PHY address of ENET0 could not found. Why ? Any idea?
02-06-2017 03:15 AM
do you see any error message when the PHY is being read?
are you able to read the correct PHY address in cascaded mode?
02-06-2017 06:55 AM