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Visitor
Visitor
584 Views
Registered: ‎10-07-2019

Ethernet SGMII design for KCU 116

Hello All,

I am using a KCU 116 FPGA and try to communicate using the ethernet port. For this I tried using 1G/2.5G Ethernet PCS/PMA or SGMII core in the IP catalog and generated the example design. However, I was not able to generate the bit stream where I received DRC NSTD-1 error for 57 out of 63 ports and and DRC UCIO-1 error for 59 out of 63 ports. 

I tried manually overriding, and generated the bit stream. This generated bit stream was programmed to my FPGA, yet I could not establish communication with the board. (I tried pinging to 192.168.0.2)

Is there a way I could find a proper working ethernet design (vivado) for this board?

Thank you!

NJ

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Xilinx Employee
Xilinx Employee
554 Views
Registered: ‎09-05-2018

Hey @najath_akram,

I think the resource you're looking for is XAPP1026. It doesn't apply to the KCU 116 specifically, so you'll have to do some porting, and it'll act more or less as a reference. But if you're pinging the board, it sounds like you want something with a processor to act as a server and handle the packets, which is what that XAPP shows how to do.

The errors you see with this IP Example Design are expected; the onus is on the user to place the pins before running bitstream generation.

Nicholas Moellers

Xilinx Worldwide Technical Support
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Visitor
Visitor
492 Views
Registered: ‎10-07-2019

Hello @nmoeller 

Thank you for the response. 

The goal of my design is to use Matlab AXI master block to work for KCU 116 board. The KCU 116 board uses a SGMII PHY and I have already developed a working design for VC 707 board (block design attached), which uses SGMII PHY as well. 

However, these two boards have two main differences as I could notice.

1. The KCU 116 board uses a TI DP83867ISRGZ PHY interface and VC 707 uses M88E1111 interfeace. 

2. VC 707 supports MIG 7 series memory interface, where KCU 116 requires DDR4 SDRAM memory interface. 

I tried porting the same design to KCU 116 (as attached schemetic). I used the user guide for the board and MIG reference design to write this constraint file. But I could not ping to the board with this design.

I think the issue is with the constraint file (content is attached as txt) which I am using to map the PHY interface. Therefore, I wanted to refer a working design to fix the issues with ethernet communication. But the example design did not serve my requirement. 

Would there be any source that I can use to use as a reference design for ethernet?

Thank you!

VC707.PNG
KCU116.PNG
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Xilinx Employee
Xilinx Employee
458 Views
Registered: ‎05-01-2013

What's the "status_vector" when the link is not up?

Have you tried GT PMA near end loopback? Can it link up in the loopback mode?

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Moderator
Moderator
455 Views
Registered: ‎08-25-2009

Hi @najath_akram ,

Please check this link for a design porting to KCU105 using board support flow:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841604/KCU105+SGMII+over+LVDS+design+creation+using+board+flow

You could try creating the same for KCU116. 

 

"Don't forget to reply, kudo and accept as solution."
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