I am using 1G/2.5G Ethernet PCS/PMA or SGMII (v 16.1) IP for SGMII to the GMII bridge.
In the project SGMII side of the IP is connected with Marvell PHY (M88E1111_BAB1C000) and the GMII side is loopback. And an Ethernet Analyzer is used for testing purpose.
IP settings is as follows:
For information, I configure the 1G/2.5G Ethernet PCS/PMA or SGMII (16.1) IP with the following parameters:
BOARD: - MDIO-> mdio mdc
- ETHERNET-> SGMII over LVDS
- DIFFCLK-> custom
Data Rate: - Select Data Rate-> 1G
Standard: - Select Standard-> SGMII
Core Functionality: - Physical interface-> LVDS Serial
- EnableAsyncSGMII-> false
- Lvds Reference clock-> 125MHz
- MDIO Management Interface-> selected
- Auto Negotiation -> selected
SGMII Operation Mode: - SGMII PHY Mode-> not selected
Shared Logic: -> Include Shared Logic in Core
Currently, for SGMII signals, we are using IOSTANDARDS as SUB_LVDS. Because LVDS is not supported for HR bank and SGMII connections are made over the HR banks.
Status: A valid is link is established between PHY and the Analyzer. But on monitoring the status vector of PCS/PMA IP it is showing Link status is not valid.
Thank you in advance.
So what're the status_vector now?
Do you enable/disable AN in the both ends?