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Visitor oanekingma
Registered: ‎11-05-2014

Ethernet SGMII to GMII bridge to GMII PHY

We are trying to implement the 'Ethernet 1000BASE-X PCS/PMA or SGMII' IP block in a Spartan 6 where we would like to IP to be used as an SGMII to GMII bridge (Coregen config attached):

[ MAC ] ---- SGMII link ---- [ SGMII / GMII bridge (IP) ] ---- GMII link ---- [ PHY ] ---- ethernet cable

The IP should support this, looking at the documentation (figure 1.8). However, when configuring the IP through Coregen, all of the comments in the example design suggest that the generated IP should be connected to a MAC on the GMII side. Additionally, the generated IP block 'gig_eth_pcs_pma_v11_5_block' shows that both the transmit clock and receive clock pins are outputs (these signals are generated by the PHY normally). Therefore I would expect them to be both set as input...


All of this leads me to believe that the IP currently works as a GMII to SGMII bridge (as depicted in figure 1.7).


My questions:

- Is there some IP configuration option that I've missed to generate the SGMII to GMII bridge mode?

- If not, can I just connect all the TXD's of my PHY to the RXD's of the IP block and vica versa and it should work?

- If so, what about the TX and RX clock outputs?


Your help is much appreciated!

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Xilinx Employee
Xilinx Employee
Registered: ‎02-06-2013

Re: Ethernet SGMII to GMII bridge to GMII PHY




Check PHY mode of operation in the below doc which meets your requirement.





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Visitor oanekingma
Registered: ‎11-05-2014

Re: Ethernet SGMII to GMII bridge to GMII PHY

Hi Satish,


It's starting to become a bit more clear... basically the example design generated is for SGMII MAC mode only and I need to adapt that to my needs for SGMII PHY mode. I will look into it more tomorrow to find out what that actually entails...


Thanks for now and if you have any tips, that would be great.


Best regards,


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