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gopal_1921ee16
Participant
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Registered: ‎01-14-2020

Ethernet access to Atlys FPGA

Dear all

Please help in accessing ethernet port of Atlys FPGA board. 

Is it possible to access ethernet port using available IP in ISE or I have to write protocol for it?

please reply if anybody has done that.

 

--

Gopal krishna

Gopal_krishna
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dpaul24
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Registered: ‎08-07-2014

@gopal_1921ee16 ,

You can generate and use (only Evaluation license is free) the TEMAC IP core for ISE in the Spartan6 FPGA.

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joancab
Advisor
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Registered: ‎05-11-2015

Yes, you can use the ethernet. There are probably a number of ways, the one that comes to my mind is to have a Microblaze processor (Linux mode) and all the lower layers built with IP cores. 

gopal_1921ee16
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Registered: ‎01-14-2020

thank you @dpaul24 

Can you please guide me how can I configure it with physical pin of FPGA?

Gopal_krishna
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dpaul24
Scholar
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Registered: ‎08-07-2014

@gopal_1921ee16 ,

Do you know how to write the constraints file where your top level design ports are mapped to the FPGA pins?

If not then please get the Xilinx ISE docs where pin mapping is explained (I have stopped using ISE a long time ago). You need to create a UCF file for your design. Xilinx uses (user constraints file) UCF to bridge the physical pin connections to top-level signals in your design. This file should be added to the project.

It looks something like this:

NET "CLK_40Mhz" TNM_NET = CLK_40Mhz;
TIMESPEC TS_CLK_40Mhz = PERIOD "CLK_40Mhz" 25 ns;
########################################################
#8+2 LED's for indication
########################################################
NET "FPGA_LED<0>" LOC = B21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<1>" LOC = B22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<2>" LOC = C21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<3>" LOC = C22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<4>" LOC = D21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<5>" LOC = D22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<6>" LOC = E22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<7>" LOC = F21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<8>" LOC = F22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<9>" LOC = G22 | IOSTANDARD = "LVCMOS33";
#######################################################
#6 FET/IGBT gate-drive FET-outputs
#######################################################
NET "FPGA_Gate1" LOC = V22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate2" LOC = W22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate3" LOC = W21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate4" LOC = Y22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate5" LOC = Y21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate6" LOC = AA22 | IOSTANDARD = "LVCMOS33";

NET "CLK_40Mhz" TNM_NET = CLK_40Mhz;
TIMESPEC TS_CLK_40Mhz = PERIOD "CLK_40Mhz" 25 ns;

 

 

 

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gopal_1921ee16
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Registered: ‎01-14-2020

@dpaul24 

Yes I know how to write constraints file.

Point is that MAC IP has multiple input/output ports. I am not getting which port should connect which physical pin.

Is only MAC IP is sufficient to access the ethernet port of FPGA??

 

Gopal_krishna
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dpaul24
Scholar
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Registered: ‎08-07-2014

@gopal_1921ee16 ,

Point is that MAC IP has multiple input/output ports. I am not getting which port should connect which physical pin.

Is only MAC IP is sufficient to access the ethernet port of FPGA??

Your question tells me that you have perhaps not understood the Data Link Layer(Layer2) and Physical Layer(Layer1) of the Ethernet protocol. Please study the Xilinx docu on the Ethernet IP core, it is really important. Focus on the chapter Example Design. If you still do not understand something there in, then please create a new thread and put a specific question.

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gopal_1921ee16
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Registered: ‎01-14-2020

Thank you @dpaul24 for your suggestion. 

I am studying TMEC ip core document  "LogiCORE IP Tri-Mode Ethernet MAC v5.4". 

I am very New in FPGA world can you please refer me some resources to get familiar with FPGA devices.

 

Gopal_krishna
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dpaul24
Scholar
Scholar
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Registered: ‎08-07-2014

@gopal_1921ee16 ,

Begin with this -  https://www.xilinx.com/support/documentation/data_sheets/ds160.pdf

https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html - Here user the filter "User Guides"

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aforencich
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Registered: ‎08-14-2013