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Visitor
Visitor
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Registered: ‎02-05-2020

Ethernet bd doesn't match example design

I'm running into a pretty weird and frustrating problem. Whenever I create the ultrascale 100G ethernet core it creates the port gt_serial_port which consists of both of the differential pairs for tx and rx. However, I am running the simplex Tx mode and in the example design the gt_rx is missing from the block and the gt_serial_port is just replaced with the gt_tx differential pair. I figured I simply could just assign the gt_rx ports to 0 since it was just transmitting data but the actual ip files gave me errors saying that they didn't have the gt_rx in their port list causing an error. I was able to go into these files outside of vivado (since in vivado they were read-only) and create the gt_rx ports in the port list which enabled the simulation to start working, but the synthesis gave me the same errors which were inside files that I can not access. Has anyone run across this problem. Its lagging the project I am working on pretty bad. 

Thanks in advance.bdbad.PNGbdgood.PNGbdissue.PNG

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Visitor
Visitor
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Registered: ‎02-05-2020

Re: Ethernet bd doesn't match example design

Also, I know that the part used, as seen in someone posting about the same problem, has an effect on this. I set the part in the example design as the xczu28dr-ffvg-1517-2-e through the parts interface and it gave the block to the right above, but if I do the eval platform with the exact same part identifier it gives me the block to the left. This is extremely confusing and I am beginning to question the compatibility of my board with the core. I guess the true issue is how to I get the ip core files to add the gt_rxp_in side of the differential pairs.
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Explorer
Explorer
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Registered: ‎08-14-2013

Re: Ethernet bd doesn't match example design

I think you have to connect the RX ports to the RX pins on the board, even if they are not connected to anything on the board. The GTY transceiver primitive has both TX and RX, and you can't just use one and leave the other disconnected from the actual chip pads. This should not affect your application in any way if those pads are not used. Now, if you need to do something different with the RX channels of those transceivers, then things get complicated - you'll need to generate the Ethernet MAC without transceivers, generate the transceivers separately with the correct settings, and make the appropriate interconnections.
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Visitor
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Registered: ‎02-05-2020

Re: Ethernet bd doesn't match example design

That is what I thought initially, but the error I get is still with the actual ethernet ip files.

files.PNG

These files to be specific. The Ethernet.vhd file instantiates the cmac_usplus_0 with the rx pins, but the cmac_usplus_0 does not have them in its port list. Both are read-only in vivado. What I did was edit them in their actual locations using a text editor which worked for simulation but failed in synthesis with the same error I got before I figured out the way to get the simulation working. It might be possible though that I can gnd out all the extra signals added in duplex mode and connect the rx pins to the board and see if works that way. For now I have switched from the eval board to the part as the target which changes the bd to not have the rx pins. Hopefully, this does not affect the end design but I will post any breakthroughs I have. Thanks for the help. 

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Explorer
Explorer
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Registered: ‎08-14-2013

Re: Ethernet bd doesn't match example design

It's entirely possible this is a Vivado bug. Have you tried generating a full-duplex core and then only connecting the TX side? It's possible the PHY layer does something annoying and prevents the TX side from working if the RX side link is not up, but it's worth a shot if there aren't any other obvious solutions.
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Moderator
Moderator
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Registered: ‎04-01-2018

Re: Ethernet bd doesn't match example design

Hi @tturner44 

I believe the configuration you have selected is Simplex TX. This will enable only TX portion of the Core and also you will see the packet generator only when example design is generated for the core. 

As per the simulation for the core when Simplex TX is selected it will generate the Partner Test Bench which is Simplex Rx which can be only used for simulation it wont be synthesized.

cmac.PNG

 Refer Page 163 and 164 of PG203. 

It is mentioned in the above Figure that Simplex TX core can be used for Simulation, Synthesis and Place & Route and Simplex RX is only used for Simulation.

As per my knowledge this is expected behaviour when Simplex Tx mode is selected in CMAC core.

 

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