02-17-2020 08:15 AM
I'm running into a pretty weird and frustrating problem. Whenever I create the ultrascale 100G ethernet core it creates the port gt_serial_port which consists of both of the differential pairs for tx and rx. However, I am running the simplex Tx mode and in the example design the gt_rx is missing from the block and the gt_serial_port is just replaced with the gt_tx differential pair. I figured I simply could just assign the gt_rx ports to 0 since it was just transmitting data but the actual ip files gave me errors saying that they didn't have the gt_rx in their port list causing an error. I was able to go into these files outside of vivado (since in vivado they were read-only) and create the gt_rx ports in the port list which enabled the simulation to start working, but the synthesis gave me the same errors which were inside files that I can not access. Has anyone run across this problem. Its lagging the project I am working on pretty bad.
Thanks in advance.
02-17-2020 02:52 PM
02-17-2020 08:26 AM
02-17-2020 02:52 PM
02-18-2020 06:16 AM
That is what I thought initially, but the error I get is still with the actual ethernet ip files.
These files to be specific. The Ethernet.vhd file instantiates the cmac_usplus_0 with the rx pins, but the cmac_usplus_0 does not have them in its port list. Both are read-only in vivado. What I did was edit them in their actual locations using a text editor which worked for simulation but failed in synthesis with the same error I got before I figured out the way to get the simulation working. It might be possible though that I can gnd out all the extra signals added in duplex mode and connect the rx pins to the board and see if works that way. For now I have switched from the eval board to the part as the target which changes the bd to not have the rx pins. Hopefully, this does not affect the end design but I will post any breakthroughs I have. Thanks for the help.
02-18-2020 12:24 PM
02-19-2020 06:18 AM
I believe the configuration you have selected is Simplex TX. This will enable only TX portion of the Core and also you will see the packet generator only when example design is generated for the core.
As per the simulation for the core when Simplex TX is selected it will generate the Partner Test Bench which is Simplex Rx which can be only used for simulation it wont be synthesized.
Refer Page 163 and 164 of PG203.
It is mentioned in the above Figure that Simplex TX core can be used for Simulation, Synthesis and Place & Route and Simplex RX is only used for Simulation.
As per my knowledge this is expected behaviour when Simplex Tx mode is selected in CMAC core.
06-18-2020 11:50 AM
The responder here doesn't understand the issue posted above, and points to an irrelevant document. The issue is that the design_1.v/vhd file includes ports that don't exist when either simplex RX or TX operation is selected. When trying to simulate or synthesize, Vivado errors out saying that the ports on the underlying block don't match the design_1 wrapper (which is created and managed by Vivado). This is a Vivado bug and has nothing to do with the operation of the packet generator. It will fail with a similar message when any simplex core is brought into the simulator.