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achopard
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Registered: ‎02-01-2021

Ethernet lwIP Echo server on Zynq7000 on RED pitaya STEMLAB 125-14

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Hello Everyone. 

I am implementing an embedded radar data processing unit on the RED pitaya board, using the onboard ADCs, then in line data-processing in the PL of the Zynq followed by an ethernet Data transfert. 

I am facing some issues for this last stage. First, a DMA data transfert is properly performed from the PL to the PS. The plan is then to read the datas in the PS to transfert them toward a computer via a direct Ethernet connection.

For this step, I have been unsuccessfully trying for quite a while to get the lwIP echo server to work on my board. First of all, the RP implemented Ethernet PHY is not supported by the lwIP echo server. An additional driver for the LANTIQ PEF 7071 ship, that I found on the RP forum (https://forum.redpitaya.com/viewtopic.php?t=1880) needs to be added in the xemacpsif_physpeed.c file.  The driver seems to work properly and sets the PHY-speed to an adequate value of 1000 after completing the speed auto-negociation. Then, looking at the PHY status register, seems to comfort the fact that the PHY has been set properly since no errors are detected, the autonegiciation successful flag is up, and it is set to operate in 1000 BaseT full-duplex mode.

 

-----lwIP TCP echo server ------

TCP packets sent to port 6001 will be echoed back

WARNING: Not a Marvell or TI or Realtek Ethernet PHY. Please verify the initialization sequence
LANTIQ Ethernet PHY detected at address 1. Launching specific initialization sequence

get_Lantiq_phy_speed : Phy 1 => Starting Autonegotiation

get_Lantiq_phy_speed phy1 Phy reset completed after 1 ms

Lantiq Mdio.MiiCtrl B300x Rst Skews Rx=1500 Tx=1500 (ps)

Lantiq Mdio.MiiCtrl 4D00x Set Skews Rx=2000 Tx=2500 (ps)

get_Lantiq_phy_speed phy1 Waiting for PHY to complete autonegotiation

get_Lantiq_phy_speed phy1 Autonegotiation successful after 3 ms MiiStatus = 000Ax

get_Lantiq_phy_speed phy1 MdioRegister 0x = 1040x

get_Lantiq_phy_speed phy1 MdioRegister 1x = 796Dx

get_Lantiq_phy_speed phy1 MdioRegister 2x = D565x

get_Lantiq_phy_speed phy1 MdioRegister 3x = A401x

get_Lantiq_phy_speed phy1 MdioRegister 4x = 0DE1x

get_Lantiq_phy_speed phy1 MdioRegister 5x = C1E1x

get_Lantiq_phy_speed phy1 MdioRegister 6x = 000Fx

get_Lantiq_phy_speed phy1 MdioRegister 7x = 2001x

get_Lantiq_phy_speed phy1 MdioRegister 8x = 4806x

get_Lantiq_phy_speed phy1 MdioRegister 9x = 0300x

get_Lantiq_phy_speed phy1 MdioRegister Ax = 2800x

get_Lantiq_phy_speed phy1 MdioRegister Bx = 0000x

get_Lantiq_phy_speed phy1 MdioRegister Cx = 0000x

get_Lantiq_phy_speed phy1 MdioRegister Dx = 0000x

get_Lantiq_phy_speed phy1 MdioRegister Ex = 0000x

get_Lantiq_phy_speed phy1 MdioRegister Fx = 3000x

get_Lantiq_phy_speed phy1 MdioRegister 10x = 8000x

get_Lantiq_phy_speed phy1 MdioRegister 11x = 0000x

get_Lantiq_phy_speed phy1 MdioRegister 12x = 0000x

get_Lantiq_phy_speed phy1 MdioRegister 13x = 0001x

get_Lantiq_phy_speed phy1 MdioRegister 14x = 8006x

get_Lantiq_phy_speed phy1 MdioRegister 15x = 0000x

get_Lantiq_phy_speed phy1 MdioRegister 16x = 0000x

get_Lantiq_phy_speed phy1 MdioRegister 17x = 4D00x

get_Lantiq_phy_speed phy1 MdioRegister 18x = 000Ax

get_Lantiq_phy_speed phy1 MdioRegister 19x = 0000x

get_Lantiq_phy_speed phy1 MdioRegister 1Ax = 3401x

get_Lantiq_phy_speed phy1 MdioRegister 1Bx = 0F00x

get_Lantiq_phy_speed phy1 MdioRegister 1Cx = 0000x

get_Lantiq_phy_speed phy1 MdioRegister 1Dx = 00AAx

get_Lantiq_phy_speed phy1 MdioRegister 1Ex = 8435x

get_Lantiq_phy_speed phy1 MdioRegister 1Fx = 0000x

 

After this PHY initialization, the echo server setup seems to follow its course up until the end :

 

link speed for phy address 1: 1000
DHCP Timeout
Configuring default IP of 192.168.1.10
Board IP: 192.168.1.10

Netmask : 255.255.255.0

Gateway : 192.168.1.1

TCP echo server started @ port 7

 

On the computer side, static address is set as follows : 

Suffixe DNS propre à la connexion. . . :
Adresse IPv6 de liaison locale. . . . .: fe80::cd8c:a129:f905:e5f4%19
Adresse IPv4. . . . . . . . . . . . . .: 192.168.1.250
Masque de sous-réseau. . . . . . . . . : 255.255.255.0
Passerelle par défaut. . . . . . . . . : 0.0.0.0

Nevertheless, it remains impossible connect in any way with this IP address (Using Putty or TeraTerm to connect to port 7 leads to connection timeout , ping the desired IP address leads to "Request timed out" and "Destination host unreachable", ...).

Inspection through Wireshark does not detect any transmission from the board IP and the "arp -a" command does not detect the board's IP : 

Interface : 192.168.1.250 --- 0x13
Adresse Internet Adresse physique Type
192.168.1.255 ff-ff-ff-ff-ff-ff statique
224.0.0.22 01-00-5e-00-00-16 statique
224.0.0.251 01-00-5e-00-00-fb statique
224.0.0.252 01-00-5e-00-00-fc statique
239.255.255.250 01-00-5e-7f-ff-fa statique

Just as if the board does not actually generate the server.

Anyone faced a similar issue on the RedPitaya board?

Is there anything else I should investigate in the Echo server example code, relative to the fact that I am using an initially non supported PHY?, beside the PHY initialization sequence?

Thank you in advance for any tips.

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achopard
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Registered: ‎02-01-2021

Hello @nanz 

Thank you again for the help you provided.

I finally managed to get it going, it was actually a wrong setting in the ethernet in the Zynq Block on the PL design. Then preventing the ETH0 to communicate properly with the lwIP software.

The PHY driver for the integrated Lantiq PHY, found on the red pitaya forum, actually works perfectly.

 

Thank you again for your help.

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nanz
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Registered: ‎08-25-2009

Hi @achopard ,

The PHY init sequence will be the 1st thing to check. Then i would recommend checking with a different link partner and check PHY status registers or test with a different ethernet cable to see if there is any situation that you can ping successfully.


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achopard
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Registered: ‎02-01-2021

Hello @nanz!

Thank you very much for your reply and the helpful insights!

The init sequence for the PHY seems to run properly since I am able to auto-negotiate properly and settle with a consistent Phy speed of 1000 and a link status stable to UP.

As described in the following link, https://forum.redpitaya.com/viewtopic.php?t=1880, the PHY driver generates the following sequence : 

- PHY reset to default state

- RX TX skew setting on register 17x

- advertise 10M / 100M / symmetrical and asymmetrical pauses

- advertise 1000M

- enable and restart autonegociation

- get speed from register MII stat register (x18)

- read all registers for control

- return speed

 

 

According to the spec sheet of the PHY (https://datasheet.octopart.com/PEF-7071-V-V1.5-Lantiq-datasheet-62314344.pdf), the status register (1x) reaches 796Dx indicating that the auto-negociation went well without any faults, the link is up and is able to communicate in 10 BaseT and 100 Base Tx. The Gigabyte status register (Ax) is also to settle to the value 7800x (slight mistake in the pervious log) ( link partner capable of 1000baseT full duplex, remote and local  receiver status of 1 and master configuration for the PHY) and the MII status register ( 18x)  reaches 0x000A for a 1000MBits/s link in full duplex with twisted-pair interface for the PHY.

Are they any other registers that could be critical for PHY setting?

When unplugging and plugging back the cable,  the link status goes down and the initiation sequence restarts properly until a link up status is reaches (comforting point for the initialization sequence). 

I noticed that in the Physical Layer Performance Status register, I have an INVALID value of (0x80) for the  "Frequency Offset of Link-Partner". I do not know if this could be one of the causes of my inability to detect the IP address on the computer side.

 

 

I also noticed that I have only one active led on the RJ45 socket (orange led that is on all the time and blinks when some transfers occur).

 

Several ethernet cables have already been tested, and communication through an 10MHz ethernet SWITCH did not solved the problem, beside validating the PHY speed auto-negociation which then settled to 10, the board IP was still inexistant on the computer side. 2 computers have been tested as well, with firewall disabled.

 

I remain stuck at a point where everything seems to run smooth on the board side with the propre initialization of the PHY but no corresponding IP address can be detected on the computer side.

Are their other points in the lwIP base code that needs to be looked at more carefully?

 

Thank you in advance for your reply. 

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nanz
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Registered: ‎08-25-2009

Hi @achopard ,

As you have PHY registers showing a linkup, 1000Mbps and full duplex, this should be a good indicator that PHY seems to be up and the init sequence as you have confirmed seems to be fine too. 

I am not sure what this means - "Physical Layer Performance Status register, I have an INVALID value of (0x80) for the  "Frequency Offset of Link-Partner"." But does it indicate an issue on the PC side or on the board side? 

For Lwip, one more thing you could test with is to enable/disable DHCP in LWIP configurations and see if that makes it better. With DHCP, it  will auto-check out an IP address for you when trying to linkup with the link partner. 


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achopard
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Registered: ‎02-01-2021

Thank you @nanz  for this reply.

DHCP does not seem to change anything. When DHCP is enable, an expected  "DHCP Timeout" message is followed by a configuration of the default IP. disabling DHCP does not seems to change anything beside skipping the DHCP step, leading to a default IP setting as well.

 

Looking at the attached part of the PHY data-sheet, Physical Layer Performance Status register invalid value would make me think that there is a problem on the PC side with an incompatibility in terms of clock frequency. Nevertheless, I don't have any way to set a proper frequency on my ETH port on the PC.

Digging further in the testing, I tried with a more advances switch, and this invalid value of 0x80 in the Physical Layer Performance Status register vanished ( 0x95e0 in the register), along with the activation of the green led that was switched off up till now. Nevertheless, still unable to detect the IP of the board on the PC side.

Could you think about a limiting factor that could give rise to this behavior?

 

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nanz
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Registered: ‎08-25-2009

Hi @achopard ,

I am not sure but it does not sound a link partner issue connected to the PHY. 

Do you have a loopback cable that you could connect externally to check if that is working? I assume PHY loopback is working fine without any issues?


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achopard
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Registered: ‎02-01-2021

Hello @nanz 

Thank you again for the help you provided.

I finally managed to get it going, it was actually a wrong setting in the ethernet in the Zynq Block on the PL design. Then preventing the ETH0 to communicate properly with the lwIP software.

The PHY driver for the integrated Lantiq PHY, found on the red pitaya forum, actually works perfectly.

 

Thank you again for your help.

View solution in original post

nanz
Moderator
Moderator
410 Views
Registered: ‎08-25-2009

Hi @achopard ,

Great you figured this out! Can you please be more specific on what the wrong setting is? 


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Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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