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Adventurer
Adventurer
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Registered: ‎09-13-2019

Ethernet simulation takes > 1ms

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I'm trying to use the Ethernet 100G core and even with the -d SIM_SPEED_UP option for xvlog, the simulation takes more 1ms in order to get rx_stat_aligned. This has been previously documented:

https://forums.xilinx.com/t5/Ethernet/Virtex-UltraScale-100G-Ethernet-SIM-SPEED-UP-not-functional/m-p/892454#M14199

 

Is there any progress in providing a shorter simulation time now or in the future ? Does xilinx plan to address this ?

This is a major bottleneck in the design workflow and it should be possible to configure the simulation to run much faster, with some to no loss of feature verification.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

Do you enable RSFEC? It takes some time to get the FEC alignment.

How long time do you get aligned now? Still needs more than 1ms?

I just created an CAUI-4 example. It takes less than 200us to get stat_rx_aligned asserted.

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-05-2018

Hey @dimitris78,

That does seem quite long, so I checked it. In Vivado 2019.1, the example design simulation with cmac and cmac_usplus IP, default settings on the IP, which SIM_SPEED_UP set, and the alignment pin came up in around 110 us. I am not sure what causes the difference. Do you change any of the parameters on the IP? Are you getting any message in the simulation log about the SIM_SPEED_UP option?

To get the simulation to run faster, you could manually reduce the alignment marker spacing by making a copy of the IP source and editing the value of CTL_RX_VL_LENGTH_MINUS1 in  cmac_usplus_0_wrapper.v. However, I would caution that there is already a loss of feature verification when the SIM_SPEED_UP option is set; further shortening of the alignment marker spacing may exacerbate these losses.

Nicholas Moellers

Xilinx Worldwide Technical Support
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Adventurer
Adventurer
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Registered: ‎09-13-2019

Hi Nicholas, 

I don't see any SIM_SPEED_UP setting. 

I have a CONFIG.FAST_SIM_MODE which I have set to 1 and a SELECTED_SIM_MODE that is set to 'rtl'.

The targeted device is the Kintex xcku11p-ffv1517-1-e and the IP is the Ultrascale+ 100G Ethernet subsystem. It's using 4 x 25.7812G physical and the GT RefClk is 156.25.

 

Thanks,

Dimitris

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-05-2018

Hey Dimitris,

I don't understand; earlier you said you were using  -d SIM_SPEED_UP option, now you don't see any SIM_SPEED_UP setting?

Nick

Nicholas Moellers

Xilinx Worldwide Technical Support
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Adventurer
Adventurer
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Registered: ‎09-13-2019

My bad, I actually went to look for it in the IP CONFIG parameters... The xvlog SIM_SPEED_UP didn't do anything when I applied it. I used the example design as well.

The reason I'm asking about the device that you used and configuration is because we've noticed very different bring up times on a different IP that uses the GT transceivers: the Aurora IP channel_up takes much longer on a Kintex than on an Artix device.

Thanks,

Dimitris

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

After you applied "-d SIM_SPEED_UP", what's the value of "CTL_RX_VL_LENGTH_MINUS1" in your simulation?

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Adventurer
Adventurer
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Registered: ‎09-13-2019

So, I re-run the simulation, and the value in the file was 16'h03FF. The cmac_usplus_v2_6_0_top is locked and I can't see it in the scope.

xvlog settings.png
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Adventurer
Adventurer
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Registered: ‎09-13-2019

Here's some more information:

Configured value for rx.png
stat rx aligned.png
Configured value for tx.png
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Xilinx Employee
Xilinx Employee
682 Views
Registered: ‎05-01-2013

Do you enable RSFEC? It takes some time to get the FEC alignment.

How long time do you get aligned now? Still needs more than 1ms?

I just created an CAUI-4 example. It takes less than 200us to get stat_rx_aligned asserted.

View solution in original post

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Adventurer
Adventurer
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Registered: ‎09-13-2019

I can confirm without RS-FEC I get start_rx_aligned in ~110us. I tried both with Kintex and Virtex FPGAs and the choice doesn't matter.

I also went back and checked the core that we used in the project where the  > 1ms time was observed and RS-FEC is enabled.

So it looks the RS-FEC setting affects the simulation time a lot.