02-28-2020 07:35 AM
Looking to run Ethernet out of the 4 SFP28 ports on the RFSoC to push towards the 100 Gb/s they are capable of together. I am using the 100G ethernet core (cmac_usplus) and have had successful simulations and have met timing for my builds. My problem now is that we are having trouble finding something to interface with through the ports. Our project is supposed to consist of running 100GbE through the 4xSFP28 cage to a QSFP28 port on a NIC which then moves it to a GPU for further processing. We reached out to a manufacturer about a cable that has 4 SFP connectors on one end and a QSFP on the other end but they seemed to believe that the cable wouldn't work do to the connection being host to host and not involving a switch in between. Looking for any advice on the hardware we should target for what is receiving the data out of the FPGA in terms of cables, NICs, or any other tips. Also, with the ethernet out of the FPGA does the ip core encapsulate that data into an ethernet frame or do I need to create the frame myself? We figured that with only two systems connected we did not need to but thought the NIC may drop it if it doesn't have a legal header. Thanks in advance for any advice, help, or links.
03-04-2020 10:31 PM
03-03-2020 11:11 PM
You don't need to send any data. IP core is able to send/receive IDLE and get the link up first.
So how about CMAC block_lock, synced and aligned signals? Does CMAC link up?
If not, you can try near end loopback test first.
03-04-2020 10:31 PM
05-15-2020 10:44 AM
06-17-2020 06:48 PM
If you have a DAC, then all of those extra pins (tx disable, rs, module detect), etc. are completely irrelevant. All of the DACs that I have seen are totally passive and directly connect the main high speed data pins together, the only other part in there would be an I2C EEPROM to identify the cable. I don't have an AN license, so I have never used AN for 10G, 25G, or 100G.
If the external loopback works, that makes me think maybe you're running at the wrong line rate or something along those lines. Have you checked to make sure the reference oscillators are configured the way they need to be?