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350 Views
Registered: ‎08-29-2019

Ethernet using internal block memory

Hi,

I want to design( Microblazed Design) Ethernet 10/100/1000 Mbps using internal Block RAM instead of DDR memory using Vivado 2018.2.

Can you please share me  any reference design files regarding this.

Thanks & Regards,

Prashanth

5 Replies
Xilinx Employee
Xilinx Employee
299 Views
Registered: ‎11-05-2019

Re: Ethernet using internal block memory

 

Hello @prashanth_jagan_491 

 

You might get hints from the posts below.

 

Example project in microblaze and Ethernet core

https://forums.xilinx.com/t5/Ethernet/Example-project-in-microblaze-and-Ethernet-core/td-p/820482

 

Thanks

Yoichi

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267 Views
Registered: ‎08-29-2019

Re: Ethernet using internal block memory

Hi,

I need a reference design regarding the Ethernet(Without using DDR memory)by using Internal Block RAM  design using MicroBlaze,Please share me reference design files.

Thanks & Regards,

Prashanth.


@katsuki wrote:

 

Hello @prashanth_jagan_491 

 

You might get hints from the posts below.

 

Example project in microblaze and Ethernet core

https://forums.xilinx.com/t5/Ethernet/Example-project-in-microblaze-and-Ethernet-core/td-p/820482

 

Thanks

Yoichi

========================================================================
This forum is based on the cooperation of everyone who participates.
Kindly note - Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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Xilinx Employee
Xilinx Employee
255 Views
Registered: ‎11-05-2019

Re: Ethernet using internal block memory

 

Hello @prashanth_jagan_491 

 

I think that it is better to remodel with reference to XAPP1026.

 

Thanks

Yoichi

 

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Scholar dpaul24
Scholar
202 Views
Registered: ‎08-07-2014

Re: Ethernet using internal block memory

@prashanth_jagan_491,

I need a reference design regarding the Ethernet(Without using DDR memory)by using Internal Block RAM design using MicroBlaze,Please share me reference design files.

Did you STUDY and FOLLOW the simulation of the TEMAC example_design from Xilinx?

If yes, then that can be the base design for your internal BRAM + uBlaze based Ethernet design.

In the xilinx example_design, you have a small size rx_fifo after the MAC in which the rx frames are kept. They are later sent out on the MAC tx line. This is what xilinx already gives you, they call it loopback module or something like that. Now modify that design so that loopback FIFO is your BRAM FIFO. You can choose to keep the FIFO size same or increase it, depending on your needs. All the uBlaze system needs to do is read out the frames from this BRAM FIFO.

There isn't any xapp for this.

1. Study the TEMAC frame loopback Xilinx example_design.

2. Study any uBlaze based design such that processor can read from a BRAM FIFO.

3. Use the knowledge learn't from 1. and 2. to design what you want to.

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Xilinx Employee
Xilinx Employee
77 Views
Registered: ‎11-05-2019

Re: Ethernet using internal block memory

 

Hello @dpaul24 

 

To the best of my knowledge, there is no such example.

 

Is the IP Example Design that comes with Vivado helpful?

UG896 Vivado Design Suite User Guide : Designing with IP

 

Thank you

Yoichi

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