02-02-2015 09:57 AM
I want to send a 10Gbps signal to KC705 evaluation board from an outer source and then loopback it to the source. I used iBERT and Transceiver cores(example design) and I saw that in iBERT project, far end PMA loopback works fine but far end PCS loopback doesn't work. In Transceiver project both of far end loopbacks doesn't work. So I have 2 question:
1- Why far end PCS Loopback doesn't work in iBERT, however PMA loopback works fine? May PCS part change the input signal?
2- Why both of far loopbacks in Transceiver project don't work?
Thanks a lot.
02-02-2015 10:55 AM
Do you have a common clock driving the refernce clock of both the transmitter and the far-end receiver when trying this test?
02-02-2015 11:13 AM
Thanks for your reply.
No, transmitter and far end receiver have different clocks. But why far end PMA loopback works good?
Can I sove this problem without common clocks or not?
02-03-2015 12:17 PM
The PMA loopback simply connects the input to the output without any clock in the system. The PCS loopback however goes into the digital domain without a common clock between the transmitter and receiver will result in errors due to the PPM offset between two different clocks.
02-03-2015 10:36 PM - edited 02-03-2015 10:40 PM
Here is what ug476 recommends for Far end PCS loopback:
If clock correction is not used, a transceiver in Far-end PCS loopback must use the same reference clock used by the transceiver that is the source of the loopback data.
Regardless of whether or not clock correction is used, the TXUSRCLK and RXUSRCLK ports must be driven by the same clocking resource (BUFG, BUFR, or BUFH).
Since IBERT does not use clock correction, it is a must to have same reference clock for both transmitter and receiver devices.
04-27-2016 03:20 AM
I'm using Aritx-7,but in vivado 2015.2,using Far-End PMA loopback,input SDI signal,sometimes SDI cannot loopback output,sometimes SDI can loopback output,can you help me with the problem? Thank you very much.
10-28-2018 09:09 PM