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Visitor
Visitor
10,576 Views
Registered: ‎01-10-2015

Far End Loopback in Transceiver and iBERT on KC705

Hi,

 

I want to send a 10Gbps signal to KC705 evaluation board from an outer source and then loopback it to the source. I used iBERT and Transceiver cores(example design) and I saw that in iBERT project, far end PMA loopback works fine but far end PCS loopback doesn't work. In Transceiver project both of far end loopbacks doesn't work. So I have 2 question:

1- Why far end PCS Loopback doesn't work in iBERT, however PMA loopback works fine? May PCS part change the input signal?

2- Why both of far loopbacks in Transceiver project don't work?

 

Thanks a lot.

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Xilinx Employee
Xilinx Employee
10,570 Views
Registered: ‎01-03-2008

Do you have a common clock driving the refernce clock of both the transmitter and the far-end receiver when trying this test?

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Visitor
Visitor
10,563 Views
Registered: ‎01-10-2015

Thanks for your reply.

No, transmitter and far end receiver have different clocks. But why far end PMA loopback works good?

Can I sove this problem without common clocks or not?

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Xilinx Employee
Xilinx Employee
10,544 Views
Registered: ‎01-03-2008

The PMA loopback simply connects the input to the output without any clock in the system.  The PCS loopback however goes into the digital domain without a common clock between the transmitter and receiver will result in errors due to the PPM offset between two different clocks.

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Moderator
Moderator
10,535 Views
Registered: ‎02-16-2010

Here is what ug476 recommends for Far end PCS loopback:
If clock correction is not used, a transceiver in Far-end PCS loopback must use the same reference clock used by the transceiver that is the source of the loopback data.
Regardless of whether or not clock correction is used, the TXUSRCLK and RXUSRCLK ports must be driven by the same clocking resource (BUFG, BUFR, or BUFH).

Since IBERT does not use clock correction, it is a must to have same reference clock for both transmitter and receiver devices.

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Visitor
Visitor
6,533 Views
Registered: ‎09-21-2011

Hi:

  I'm using Aritx-7,but in vivado 2015.2,using Far-End PMA loopback,input SDI signal,sometimes  SDI cannot loopback output,sometimes SDI can loopback output,can you help me with the problem? Thank you very much.

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Explorer
Explorer
909 Views
Registered: ‎10-22-2018

Hi,I have a similar problem.
In my opinion, in the near-end test: PCS loopback belongs to the inner layer, PMA loopback belongs to the outer layer,
but my test result is that the near-end PCS has a high bit error rate (e-2), the near-end PMA test error BER can be up to (e-13).
Then, after I connected the fiber self-receiving (RX-TX), the near-end PCS bit error rate test was correct.

Also, I would like to ask, in the IBERT test, the difference between the fast_clk mode and the PBRS mode in the TX/RX pattern?
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