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Observer
Observer
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Registered: ‎05-10-2019

GEM EMIO on Ultrazed Question

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When Ultrascale+ GEM is configured in Vivado the dialog shows rgmii_txd[0..3] and rgmii_rxd[0..3], but if I try to use EMIO connection rgmii immediately loses 'r' and I have 8 more pins: gmii_txd[0..7] and gmii_txd[0..7]. Is it possible to configure RGMII on EMIO?

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

I would select in the Gmii to Rgmii settings under the "Shared Logic" tab to "Include Shared Logic in Core" so that the clocking is all handled under the hood.  You are correct that the clocking expects the 2.5, 25, or 125 MHz.

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

You can utilize the GMII-to-RGMII LogiCORE IP (PG160; v4.1) in the Programmable Logic (PL).

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Observer
Observer
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Registered: ‎05-10-2019

Thanks, I have another simple question: after I dropped GMIItoRMII IP to the block design, the connection automation created three ClockWizard IPs, all three 100MHz. It looks like they are supposed to be 2.5, 25 and 125 MHz?

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Xilinx Employee
Xilinx Employee
314 Views
Registered: ‎11-30-2007

I would select in the Gmii to Rgmii settings under the "Shared Logic" tab to "Include Shared Logic in Core" so that the clocking is all handled under the hood.  You are correct that the clocking expects the 2.5, 25, or 125 MHz.

View solution in original post