02-05-2020 03:33 AM
We are interfacing a custom Tri-speed MAC to Xilinx GMII to SGMII bridge. We are able to get it to simulate at Gigabit rate. (data packets being exchanged between DUT and testbench VIP in full duplex mode)
We are now trying to simulate at 10 and 100 Mbps speed. We observed that the bridge has inputs spee_is_100 and speed_is_10_100. However when we set these bits for 100Mbps, output clock is still 125MHz.
From the comments in tx/rx_rate_adapt modules, it seems that the MAC's GMII interface should still operate at gigabit rate (125MHz, 8-bit), and the data will be replicated 10 times for 100Mbps and 100 times for 10 Mbps. However my custom MAC speed should still be 100/10 Mbps.
Does this mean, I need to gate 125MHz free running clock with the clock enables generated in the adapt modules and use this gated clock for MAC Tx/Rx GMII/MII interfaces ?
Also, this means, MAC sends data at gated 125MHz clock, adapt module samples data at free running 125MHz clock, but uses only one sample every 10 clocks ? Is this right visualization ?
Sandeep J. Sathe
02-09-2020 07:25 PM
Thanks for your reply. But ...
1. Our custom MAC requires 25 MHz clock when in 100 Mbps mode, and 2.5MHz clock when in 10Mbps mode, but from the GMII to SGMII bridge, I see a pulse every 10 clocks of 125MHz, which becomes 12.5MHz, which is half of what our MAC requires.
We are now driving the 125MHz free running clock to an MMCM and bringing out 125MHz, 25MHz and 2.5MHz clocks out from MMCM. (Well, actually MMCM min clock is 6MHz. So we are bringing out 10MHz and dividing it twice using CLB Flops) We are driving all these clocks to BUGFMUX where mux select is controlled by etheret speed.
Any comments on this implementation ? Do you wish to suggest any alternate solution ?
Sandeep J. Sathe
02-11-2020 01:50 PM
You could use a state machine and an ODDR flip flop to produce the correct clock period from 125 MHz without using any PLLs. See https://github.com/alexforencich/verilog-ethernet/blob/master/rtl/rgmii_phy_if.v for how to do that.