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kinkeads
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Registered: ‎12-20-2010

GMII to SGMII bridge IP: mdio_t_in port usage

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I am using the "1G/2.5G Ethernet PCS/PMA or SGMII" core in a Ultrascale+ MPSoC as a GMII to SGMII bridge to an Ethernet SGMII PHY (T.I. DP83867E). 

On the core, I have enabled the external management interface, which provides the ext_mdc, ext_mdio, and mdio_t_in ports for communicating with an external PHY.   What is the purpose of the mdio_t_in port?   The PG047 datasheet says it should be driven by the GEM, but I see no matching port available on the GEM.  

Please clarify how mdio_t_in should be driven.

 

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kinkeads
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Registered: ‎12-20-2010

The mdio_t_in should be driven by the PS GEM mdio_t port.   On the 1G/2.5G Ethernet PCS/PMA core the mdio_t_in  passes through to the ext_mdio_t output.  So, you can use ext_mdio_t to control a tri-state buffer on the MDIO bidirectional line to an external PHY.

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nanz
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Registered: ‎08-25-2009

Hi @kinkeads ,

Can you please send a screenshot on which exact pin you are talking about? Is it MDIO interface to PS-GEM or MDIO interface to PHY?


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miker
Xilinx Employee
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Registered: ‎11-30-2007

@kinkeads 

You can utilize the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP (PG047; v16.1) in a Vivado IPI Block Design.  You can drop down a Zynq UltraScale+ MPSoC IP and a 1G/2.5G Ethernet PCS/PMA or SGMII IP and take advantage of the automation to quickly visualize the connections from the PS-GEM EMIO-MDIO to the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP.

The PS-GEM EMIO-MDIO are assuming they will connect to an IOBUF which includes in input,  output, and tristate connection.  However, the SGMII IP has the interface to easily accept EMIO-MDIO connection directly from PS-GEM.

forums_psgem_mdio.png

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kinkeads
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Yes, I have the ENET MDIO bus (mdc, mdio_i, mdio_o, mdio_t) connected as shown in your screen capture.   But, there is an input port named mdio_t_in that I do not know it's function.  I have highlighted the port in the screen capture below.   I am using Vivado 2019.1.

Selection_003.png

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miker
Xilinx Employee
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Registered: ‎11-30-2007

@kinkeads

Sorry, I missed that.  Since you have enabled the MDIO Management Interface for External PHY, you will need to control the tri-state for the external MDIO interface versus the MDIO interface from the PS-GEM to the 1G/2.5G Ethernet PCS/PMA or SGMII IP.

I utilized a PS-GPIO to drive the mdio_t_in and you can see the synthesized path below.

forums_sgmii_mdio_t_in.png

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kinkeads
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Thanks for the quick reply.  Does Petalinux support MDIO communications to the external PHY with the PS-GPIO controlling the tri-state buffer?

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miker
Xilinx Employee
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Registered: ‎11-30-2007

@kinkeads 

Linux drivers are not my expertise but you can view the PS-GEM Macb driver on the Xilinx Wiki:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841740/Macb+Driver#MacbDriver-CommonMDIODT

It appears that it does... however, I can't say for certain.

forums_macb_linux_driver.png

 

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kinkeads
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I don't see how controlling mdio_t_in from the GPIO pin will work since mdio_t_in must be synchronized closely to the data stream on the bidirection mdio bus.  For example, when the STA reads a PHY status register, the STA first transmits the register address to the PHY over the bidirectional bus, so the tri-state enable must be held high.  Then, during the turn-around (TA) cycle, the the tri-state enable must be toggled low to allow the PHY to transmit the register data back to STA.  

To control the tri-state enable with a GPIO, the software drivers will need to know when the turn-around (TA) cycle occurs and which GPIO is controlling the tri-state enable.  

kinkeads_0-1611251024017.png

During our testing, using a GPIO to control mdio_t_in did not work.  The driver fails to read the PHY status register to determine if the link is up/down.

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miker
Xilinx Employee
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Registered: ‎11-30-2007

@kinkeads 

Sorry, I didn't mean to suggest that the PS GPIO was the solution to drive the MDIO... I just wanted to implement a driver so I could view the mdio_t_in path to verify it was what I expected.

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kinkeads
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The mdio_t_in should be driven by the PS GEM mdio_t port.   On the 1G/2.5G Ethernet PCS/PMA core the mdio_t_in  passes through to the ext_mdio_t output.  So, you can use ext_mdio_t to control a tri-state buffer on the MDIO bidirectional line to an external PHY.

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