10-10-2008 12:21 AM
I generated the GTP_DUAL_FAST smartmodel using xilinx 10.1ISE and integrated into my design. I am using VCS/Y-2006.06-SP2-2 version. When we run the simulation it is found that PLLLKDET does go high initially but after some time returns to 0. When the PLLLKDET was high the TXOUTCLK was in tristate and when returned to 0 TXOUTCLK was 0. I dont see clock on TXOUTCLK as the spec says. All the RESET inputs and CLKIN is driven as per the spec, RESETDONE is always 0.
The SIM params are configured as below:
- SIM_MODE = FAST
- SIM_GTP_RESET_SPEEDUP = 1
Please help me resolve this issue.
10-10-2008 08:21 AM
I would check the following:
- Clock - Make sure that it is consistent, at the frequency that you configured the GTP for, and that you don't get weird blips due to rounding of the clock period.
-Resets - GTPRESET should be toggled at the beginning of the simulation. It can take a long time to lock (in hardware up to 160 us, simulation it will depend on the SIM_GTPRESET_SPEEDUP attribute but I would estimate that you should run the sim for at least 8 us). Other resets can affect RESETDONE. The Virtex-5 RocketIO GTP Transceiver User Guide (http://www.xilinx.com/support/documentation/user_guides/ug196.pdf) has a table with all the resets that shows which affect RESETDONE.
-TXPOWERDOWN - Make sure these signals are defined at the beginning of the simulation.
10-13-2008 05:20 AM
10-13-2008 08:26 AM
Just for future reference I meant 80 us, not 8.