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Participant a4speaker
Participant
13,790 Views
Registered: ‎08-16-2011

GTP IBERT loopback

I need to check GTP link integrity on AC701 board. I read document xtp224.pdf (AC701 GTP IBERT Design Creation) while using vivado 2013.3.

 

I downloaded  RDF0222 - AC701 GTP IBERT Design Files (2013.3 C) zip and did waht was written in xtp224.pdf

 

In the design folder,  i noted in xdc file that no lines are there to connect TXP,TXN with RXP and RXN respectively.

 

In serial IO analyzer layout mode, the link is up with 6.25 gbps while there is no loopback.

Link is up : for near end PCS and PMA loopback modes.

no link : when far end PCS and far end PMA loopbacks are done.

 

Can anyone tell me do i need to put TX,RX pin locations in xdc file or if somethiing else is wrong?

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17 Replies
Community Manager
Community Manager
13,781 Views
Registered: ‎07-23-2012

Re: GTP IBERT loopback

Hi a4speaker,

You need to use SMA cables to connect TX/RX.

That could the reason why you don't see the links to be up.

Regards,
KRishna
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Xilinx Employee
Xilinx Employee
13,781 Views
Registered: ‎08-01-2012

Re: GTP IBERT loopback

Verify whether you are applying reset in IBERT after changing entries.

 

Also use IBERT design assistant ARhttp://www.xilinx.com/support/answers/33793.html to solve the issue

 

Also the following AR http://www.xilinx.com/support/answers/54139.html helps to verify switch and & jumper settings and to check board problems if exists

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Participant a4speaker
Participant
13,770 Views
Registered: ‎08-16-2011

Re: GTP IBERT loopback

I am using SMA cables tested for upto 6 GHz  on network analyzer

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Community Manager
Community Manager
13,766 Views
Registered: ‎07-23-2012

Re: GTP IBERT loopback

Hi a4speaker,

Which revision of AC701 board are you using?

The GT attributes vary with the silicon version. If possible, try to generate IBERT core and see if the error gets resolved or not.

Regards,
Krishna
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Xilinx Employee
Xilinx Employee
13,760 Views
Registered: ‎07-31-2012

Re: GTP IBERT loopback

Hi,

 

The FAR end loopback mode does not work for a single TX and RX. the FAR end loopback modes indicate a loopback as TX(FPGA1)-> RX(FPGA2) - > looped back through either PCS/PMA -> TX(FPGA2) -> back into the RX(FPGA1 where frame check is done)

 

By connecting a TXP/N to the RXP/N, you are just looping back externally. You should give the mode as "None" to check for the external loopback. Check and let me know if the None mode does not show the required line rate.

Thanks,
Anirudh

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Participant a4speaker
Participant
13,755 Views
Registered: ‎08-16-2011

Re: GTP IBERT loopback

By selecting NONE as loopback mode, i get link up with BER = 6.2E-13 . I am attaching the eye scan result.

eye.png
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Participant a4speaker
Participant
13,753 Views
Registered: ‎08-16-2011

Re: GTP IBERT loopback

Krishna I am using revision 2 of board

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Participant a4speaker
Participant
13,746 Views
Registered: ‎08-16-2011

Re: GTP IBERT loopback

Is this link robust for implemeting Aurora?

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Participant a4speaker
Participant
13,743 Views
Registered: ‎08-16-2011

Re: GTP IBERT loopback

I need to iimplement aurora core on AC701.

 

TXRESETDONE and RXRESETDONE are 1 but channel_up and lane_up are 0. Can this be related to link training or something related to link?

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Xilinx Employee
Xilinx Employee
11,470 Views
Registered: ‎07-31-2012

Re: GTP IBERT loopback

Hi,

 

Since the IBERT shows the link is up, that means the data is being recived correctly at the RX irrespective of the BER values. You can depend on the IBERT test on the signal integrity of the link. On the Aurora Problem, did you simulate your design and check? Does the simulation also show the lane up/channel up as 0?

 

Thanks,
Anirudh

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Participant a4speaker
Participant
11,468 Views
Registered: ‎08-16-2011

Re: GTP IBERT loopback

I ran simulation in questasim for 3000 microseconds and results are same. tx and rx resetdone are high and lane up and channel up low. The only change in example design is that i have given init_clk to the design which is generated by a pll (125 MHz input, 50 MHz output) and not from fpga pins

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Moderator
Moderator
11,415 Views
Registered: ‎02-16-2010

Re: GTP IBERT loopback

you should be holding the pma_init HIGH until the init_clk has become stable. if pma_init is released before init_clk has become stable, this could be problematic. Please ensure this.
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Participant a4speaker
Participant
11,410 Views
Registered: ‎08-16-2011

Re: GTP IBERT loopback

where is this pma_init signal?  is this exact name? couldnt find with even ultrafind

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Moderator
Moderator
11,407 Views
Registered: ‎02-16-2010

Re: GTP IBERT loopback

Sorry..pma_init is used with 64B66B core.

pma_init is the gt_reset signal for 8B10B core.
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Participant a4speaker
Participant
11,405 Views
Registered: ‎08-16-2011

Re: GTP IBERT loopback

gt_reset is applied when pll locked signal is up. It is stable for 6 init_clk cycles

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Moderator
Moderator
11,399 Views
Registered: ‎02-16-2010

Re: GTP IBERT loopback

This is good.

Could you track the lane_init_sm in simulation and check where it is stuck?

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Participant a4speaker
Participant
11,396 Views
Registered: ‎08-16-2011

Re: GTP IBERT loopback

I am attaching the waveform. Magenta are states of lane_init_sm. While tracking the RESET back, it is coming from channel_init_sm and responsible signals are in yellow color.

Untitled.png
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