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7,979 Views
Registered: ‎02-19-2014

GTX byte order on RX side, issue with RXOUTCLK ?

Dear all,

I'm using an open source IP to do SRIO exchange. I used the MGT wizard 7 to generate a core able to do 4x bonding.
I'm at the behavioral simulation stage. I have connected twice the same IP back-to-back to test synchronization.
During the initialization phase, the exact same sequence is send by both instances (see TOPx TXData_hi and TXData_lo).
But on the receiving side, bytes are reversed as soon as the GTX is starting to generate data.

From the various post in the forums, I tried to look if the clocks are correctly used:
    - In the wizard my Line Rate is set to 2.5 Gbps and the Reference clock is define to 250 Mhz for TX and RX.
    - TX clock source is set to REFCLK0_Q0
    - in Synchronization and clocking I use TXPLLREFCLK and RXOUTCLK for RXUSRCLK.
    - I checked in the generated code, I have
        --------------- Receive Ports - RX Fabric Output Control Ports -------------
        RXOUTCLK                        =>      rxoutclk_out,
        RXOUTCLKFABRIC                  =>      open,
        RXOUTCLKPCS                     =>      open,
        RXOUTCLKSEL                     =>      "010",
        ---------------------- Receive Ports - RX Gearbox Ports -----------------

    as far I understood, I should used the CDR.

But from the various post, it seems I'm not used the CDR....
I was expected to have the RXUSRCLK2 with a small phase difference but in the simulation, they are strictly phase with the reference clock provided. To check that, I added in the test bench an artificial delay, in the TX/RX line with:
    busRX_02_p(0) <= transport busTX_01_p(0) after 2 ns;    
    busRX_02_n(0) <= transport busTX_01_n(0) after 2 ns;        

But the reference clock provided and the RXUSRCLK2 are still in phase. When I do that, the _second_ instance of the IP also displays the bytes in the wrong order (thus making both instances displaying in the same order)

Where do I need to look for ? Is there something I miss as I generated the wizard asking for a multi-lane, but I'm testing the 1x degraded mode ? Bonding is ok as only individual byte are considered.

 

Thanks for your help

 

Arnaud

RXDATA1.png
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Moderator
Moderator
7,923 Views
Registered: ‎02-16-2010

Re: GTX byte order on RX side, issue with RXOUTCLK ?

Check the byte alignment section and the status signals of this block. What are the settings chosen for internal data width, ALIGN_COMMA_WORD?

Are you simulating the example design of GT wizard?

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