10-07-2018 05:15 AM
i am trying to interface custom MAC which has GMII interface to SGMII ip core. we are using VCU118 kit
in the design MAC requires clk frequencies 2.5 Mhz, 25 Mhz and 125 Mhz for 10/100/1000 mbps respectively.
but SGMII ip core generates 1.25 Mhz , 12.5 Mhz and for 1000 mbps it is tied low
i am trying use Clocking wizard to double the frequency but minimum input frequency is 10 Mhz but i have to give 1.2Mhz/12.5 Mhz as input to generate 2.5 mhz /25 Mhz.
please let me know how can i do this
10-07-2018 07:44 AM
the clocking wizard uses the DLL / PLL in the chip
These are typically used to increase / decrease the input clock to the design.
I would suggest you don't want to run your design at 1.25 MHz,
Is this block your using all inside the same fpga ?
Are you wanting to send th elcok to this block ?
if so whats your system clock in the fpga ?
can you divide down off that ,
10-07-2018 08:32 PM
Thank you for the response
the sgmii ip core is the who is generating the clocks
it genarates 1.25 Mhz, 12.5 Mhz and 0 for 10/100/1000 Mbps
but depending upon the speed i need double the input frequency
i.e. i need 2.50 Mhz, 25 Mhz and 125 Mhz. for 10/100/1000
i am using vcu118 kit whose system clock 300, but to the sgmii ip core it is given the clock 125 Mhz
please let me know how to generate these clocks.....
10-08-2018 09:15 AM
so what do these clocks mean / why do yo uneed to use them as clocks ?
are they the ones the data is sent out of the IP on ?
if so then you have a source synchronous interface,
how about a nice picture,