06-28-2020 11:48 PM
We have implemented a 10g design for both zcu102 and our custom board. We have two of each board so we tested the designs first with the similar boards and it worked almost flawlessly. However, whenever we tried to test between our board and that of zcu102, the rx block could not receive a lock. I then checked the following registers
1. 0404 (sta_rx_status_reg1) = 0x000000C0 2. 040c (stat_rx_block_lock) = 0x00000000
As you can see from the output of 0404, 0xC0 means
Now here is the clock set up for the GT
In the Linux kernel, I enabled Xilinx PHYs and disabled AXI_DMAs together with other settings suggested in the Xilinx wiki for Axi_ethernet (the Rx block locks when we test similar boards)
I should also mention that the errors persisted even after I reset the gt registers. Now, I am lost for options. What could possibly be wrong?
07-01-2020 10:39 AM
Hi @alexkeys ,
RX local fault indicates that the receiver is not up and operational. Most likely causes for an rx local fault are:
Have you been able to track down on different stages and check where might be stuck?
07-01-2020 11:30 PM
1. Create 2 IBERT designs and check if they can link up with the custom board and ZCU120
2. Please make sure both designs are run at 10.3125Gbps. For example, run functional simulation and check TXP/N rate in it
3. GT locations are set correctly and P/N polarity are not inverted on board