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tkolcak
Observer
Observer
230 Views
Registered: ‎09-21-2018

Help for GT Ref Clk of 10G/25G Eth Subsystem Design

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Hello,

When using this IP both in board flow (investigating an O-RAN example design for ZCU11) and device flow (when I created a blank design for a device with GTY), I cannot see 390.625 as GT Ref clk option when IP is configured with below options:

Core: Ethernet MAC + PCS/PMA 64 bit

Speed : 25.87125G

GT Ref Clk that is presented on IP UI is 156.25 (and some other values starting from  161.13.. to 322.26)

Per user guide pg210, I was expecting IP will use a 390.625 MHz refclk for 25G operation. What is the reason for this difference and could anyone help me to understand the requirement of GT Ref Clk for 25G MAC + PCS/PMA operation ?

Thanks

 

 

 

 

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guozhenp
Xilinx Employee
Xilinx Employee
129 Views
Registered: ‎05-01-2013

In PG210, 390MHz refer to core clock, not GT Ref Clk.

PG210 also has Table299 to show the available GT Ref Clk for 10G/25G IP core. There's no 390MHz at the moment.

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guozhenp
Xilinx Employee
Xilinx Employee
130 Views
Registered: ‎05-01-2013

In PG210, 390MHz refer to core clock, not GT Ref Clk.

PG210 also has Table299 to show the available GT Ref Clk for 10G/25G IP core. There's no 390MHz at the moment.

View solution in original post

tkolcak
Observer
Observer
100 Views
Registered: ‎09-21-2018

Thank you @guozhenp 

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