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7,898 Views
Registered: ‎09-29-2009

Help implementing RGMII on the ML510

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Hello,

I am trying to convert from MII to RGMII for my TEMAC on a ML510 board using EDK 11.4.  I can follow most of the scattered and inconsisten documentation up until modification of the ucf file.  Below has been my course of action so far, with questions peppered throughout.  Has anyone successfully done this?  Essentially, my ucf file is messed up and I'm not sure how to fix it.

 

Thanks, for any help,

 

Brennon

 

-------

 

The base system builder assumes the MII interface is desired.  I found the 10.3 guide (ml510_bsb1_ppc440_std_ip_addition.pdf [pages 20-30]) to convert from MII to RGMII.  This guide assumes interrupts.

Are interrupts required for the TEMAC in RGMIII mode?
Is there a way to specify RGMII in the BSB so the mhs and ucf files are correctly generated?


Here are the steps I take:

1) Build system in BSB to include interrupts with TEMAC
2) Change TEMAC to RGMIIv2, C_NUM_IDELAYCTRL=2, and TX/RX FIFO Depth of TEMAC0 = 32768B according to the ml510_bsb1_ppc440_std_ip_addition.pdf documentation.  Then, I set C_IDELAYCTRL_LOC=IDELAYCTRL_X0Y3-IDELAYCTRL_X1Y4 according to v5_hard_rgmii_mhs.txt found in the zip file in Answer Record #32713.
    
    Is the C_IDELAYCTRL_LOC value of IDELAYCTRL_X0Y3-IDELAYCTRL_X1Y4 correct for the 510?  
 
3) Check Clock Generator to make sure CLKOUT3 is set to 125 MHz
4) Delete MII external ports in external ports section
5) Make GMIII ports external in temac section

The v5_hard_rgmii_mhs.txt documentation suggests for the temac ports:
    
    PORT GTX_CLK_0 = clk_125_0000MHzPLL0
    PORT REFCLK = clk_200_0000MHz
    
However, mine are reversed:

    PORT GTX_CLK_0 = clk_125_0000MHz
    PORT REFCLK = clk_200_0000MHzPLL0

    Does that matter?

6) Build the file and get errors about the fpga_0_Hard_Ethernet_MAC_MII nets in the ucf file, so I comment them out by placing a # sign in front of them.

#Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<3> LOC=AN31  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
#Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<2> LOC=AR32  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
#Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<1> LOC=AP32  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
#Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<0> LOC=AR33  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
#Net fpga_0_Hard_Ethernet_MAC_MII_TX_EN_0_pin LOC=AP31  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
#Net fpga_0_Hard_Ethernet_MAC_MII_TX_ER_0_pin LOC=AT31  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
#Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<3> LOC=AM33  |  IOSTANDARD = LVCMOS25;
#Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<2> LOC=AK33  |  IOSTANDARD = LVCMOS25;
#Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<1> LOC=AJ33  |  IOSTANDARD = LVCMOS25;
#Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<0> LOC=AJ32  |  IOSTANDARD = LVCMOS25;
#Net fpga_0_Hard_Ethernet_MAC_MII_RX_DV_0_pin LOC=AN33  |  IOSTANDARD = LVCMOS25;
#Net fpga_0_Hard_Ethernet_MAC_MII_RX_ER_0_pin LOC=AP33  |  IOSTANDARD = LVCMOS25;
#Net fpga_0_Hard_Ethernet_MAC_MII_RX_CLK_0_pin LOC=J17  |  IOSTANDARD = LVCMOS25;
#Net fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin LOC=M26  |  IOSTANDARD = LVCMOS25;


What are the new constraints for the Ethernet pins? (which are not included in the v5_hard_rgmii_ucf.txt file found in AR# 32713).   The v5_hard_rgmii_ucf.txt file states that "The constraints for the Ethernet pins themselves are not included here."

I Copied in the constraints from ml510_bsb_system.ucf found in the zip file ml510_bsb1_std_ip_ppc440.zip:

NET Hard_Ethernet_MAC_RGMII_TXD_0_pin<3> LOC = AN31 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
NET Hard_Ethernet_MAC_RGMII_TXD_0_pin<2> LOC = AR32 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
NET Hard_Ethernet_MAC_RGMII_TXD_0_pin<1> LOC = AP32 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
NET Hard_Ethernet_MAC_RGMII_TXD_0_pin<0> LOC = AR33 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
NET Hard_Ethernet_MAC_RGMII_TX_CTL_0_pin  LOC = AP31 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
NET Hard_Ethernet_MAC_RGMII_TXC_0_pin LOC = AM31 | IOSTANDARD =LVCMOS25 | SLEW = FAST | DRIVE = 6;
NET Hard_Ethernet_MAC_RGMII_RXD_0_pin<3> LOC = AM33 | IOSTANDARD=LVCMOS25;
NET Hard_Ethernet_MAC_RGMII_RXD_0_pin<2> LOC = AK33 | IOSTANDARD=LVCMOS25;
NET Hard_Ethernet_MAC_RGMII_RXD_0_pin<1> LOC = AJ33 | IOSTANDARD=LVCMOS25;
NET Hard_Ethernet_MAC_RGMII_RXD_0_pin<0> LOC = AJ32 | IOSTANDARD=LVCMOS25;
NET Hard_Ethernet_MAC_RGMII_RX_CTL_0_pin  LOC = AN33 | IOSTANDARD=LVCMOS25;
NET Hard_Ethernet_MAC_RGMII_RXC_0_pin LOC=J17 | IOSTANDARD=LVCMOS25;


Then I get the error messages:

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_gmii_client_clk_rx0"  =
   PERIOD "gmii_client_clk_rx0" 7500 ps HIGH 50 %;> [system.ucf(66)]: Unable to
   find an active 'TNM' or 'TimeGrp' constraint named 'gmii_client_clk_rx0'.

ERROR:ConstraintSystem:58 - Constraint <NET "*Hard_Ethernet_MAC/MII_RX_CLK_0*"  
              TNM_NET = "phy_clk_rx0";> [system.ucf(69)]: NET
   "*Hard_Ethernet_MAC/MII_RX_CLK_0*" does not match any design objects.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP  "mii_clk_phy_rx0"         =
   "phy_clk_rx0";> [system.ucf(70)]: Unable to find an active 'TNM' or 'TimeGrp'
   constraint named 'phy_clk_rx0'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_mii_clk_phy_rx0"      =
   PERIOD "mii_clk_phy_rx0" 40000 ps HIGH 50 %;> [system.ucf(71)]: Unable to
   find an active 'TNM' or 'TimeGrp' constraint named 'mii_clk_phy_rx0'.

ERROR:ConstraintSystem:58 - Constraint <NET "*Hard_Ethernet_MAC/MII_TX_CLK_0*"
   TNM_NET       = "clk_mii_tx_clk0";> [system.ucf(74)]: NET
   "*Hard_Ethernet_MAC/MII_TX_CLK_0*" does not match any design objects.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_mii_tx_clk0"          =
   PERIOD "clk_mii_tx_clk0" 40000 ps HIGH 50 %;> [system.ucf(75)]: Unable to
   find an active 'TNM' or 'TimeGrp' constraint named 'clk_mii_tx_clk0'.

ERROR:ConstraintSystem:58 - Constraint <INST "*mii0*RXD_TO_MAC*"    IOB = TRUE;>
   [system.ucf(78)]: INST "*mii0*RXD_TO_MAC*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*mii0*RX_DV_TO_MAC"   IOB = TRUE;>
   [system.ucf(79)]: INST "*mii0*RX_DV_TO_MAC" does not match any design
   objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*mii0*RX_ER_TO_MAC"   IOB = TRUE;>
   [system.ucf(80)]: INST "*mii0*RX_ER_TO_MAC" does not match any design
   objects.

ERROR:ConstraintSystem:58 - Constraint <NET
   "fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin(?)"  TNM = "mii_rx_0";>
   [system.ucf(85)]: NET "fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin(?)" does not
   match any design objects.

ERROR:ConstraintSystem:59 - Constraint <NET
   "fpga_0_Hard_Ethernet_MAC_MII_RX_DV_0_pin"   TNM = "mii_rx_0";>
   [system.ucf(86)]: NET "fpga_0_Hard_Ethernet_MAC_MII_RX_DV_0_pin" not found.
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <NET
   "fpga_0_Hard_Ethernet_MAC_MII_RX_ER_0_pin"   TNM = "mii_rx_0";>
   [system.ucf(87)]: NET "fpga_0_Hard_Ethernet_MAC_MII_RX_ER_0_pin" not found.
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <TIMEGRP "mii_rx_0" OFFSET = IN 10 ns
   VALID 20 ns BEFORE "fpga_0_Hard_Ethernet_MAC_MII_RX_CLK_0_pin";>
   [system.ucf(89)]: NET "fpga_0_Hard_Ethernet_MAC_MII_RX_CLK_0_pin" not found.
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem:168 - Constraint <TIMEGRP "mii_rx_0" OFFSET = IN 10 ns
   VALID 20 ns BEFORE "fpga_0_Hard_Ethernet_MAC_MII_RX_CLK_0_pin";>
   [system.ucf(89)]: This constraint will be ignored because NET
   "fpga_0_Hard_Ethernet_MAC_MII_RX_CLK_0_pin" could not be found or was not
   connected to a PAD.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "mii_rx_0" OFFSET = IN 10 ns
   VALID 20 ns BEFORE "fpga_0_Hard_Ethernet_MAC_MII_RX_CLK_0_pin";>
   [system.ucf(89)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync'
   constraint named 'mii_rx_0'.

ERROR:ConstraintSystem:58 - Constraint <INST "*mii0*MII_TXD_?"      IOB = TRUE;>
   [system.ucf(92)]: INST "*mii0*MII_TXD_?" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*mii0*MII_TX_EN"      IOB = TRUE;>
   [system.ucf(93)]: INST "*mii0*MII_TX_EN" does not match any design objects.
   
   .
   .
   .

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8,602 Views
Registered: ‎09-29-2009

Re: Help implementing RGMII on the ML510

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Finally figured it out...

 

 

Converting from MII to RGMII v2.0 for the Virtex-5 ML510

 

1) Configure HARD_ETHERNET_MAC IP

C_NUM_IDELAYCTRL=1
C_IDELAYCTRL_LOC=NOT_SET
Physical Interface Type = RGMII V2.0

2) Modify the MHS file

Remove all MII* from external ports

Add:
    PORT Hard_Ethernet_MAC_RGMII_TXD_0_pin = Hard_Ethernet_MAC_RGMII_TXD_0, DIR = O, VEC = [3:0]
    PORT Hard_Ethernet_MAC_RGMII_TXC_0_pin = Hard_Ethernet_MAC_RGMII_TXC_0, DIR = O
    PORT Hard_Ethernet_MAC_RGMII_TX_CTL_0_pin = Hard_Ethernet_MAC_RGMII_TX_CTL_0, DIR = O
    PORT Hard_Ethernet_MAC_RGMII_RXD_0_pin = Hard_Ethernet_MAC_RGMII_RXD_0, DIR = I, VEC = [3:0]
    PORT Hard_Ethernet_MAC_RGMII_RX_CTL_0_pin = Hard_Ethernet_MAC_RGMII_RX_CTL_0, DIR = I
    PORT Hard_Ethernet_MAC_RGMII_RXC_0_pin = Hard_Ethernet_MAC_RGMII_RXC_0, DIR = I
   
In the xps_ll_temac section of the MHS file, the PORT REFCLK must be connected to a 200MHz clock.  The name may be different between designs.

Add:
    PORT GTX_CLK_0 = clk_125mhz
    PORT REFCLK = clk_200_0000MHzPLL0
    PORT RGMII_RXD_0 = Hard_Ethernet_MAC_RGMII_RXD_0
    PORT RGMII_RX_CTL_0 = Hard_Ethernet_MAC_RGMII_RX_CTL_0
    PORT RGMII_RXC_0 = Hard_Ethernet_MAC_RGMII_RXC_0
    PORT RGMII_TXC_0 = Hard_Ethernet_MAC_RGMII_TXC_0
    PORT RGMII_TX_CTL_0 = Hard_Ethernet_MAC_RGMII_TX_CTL_0
    PORT RGMII_TXD_0 = Hard_Ethernet_MAC_RGMII_TXD_0
   
In the clock_generator section, a 125MHz clock must be added.  The number of the clock depends on the number of other clocks in your design.  Since four clocks already existed, the new one is C_CLKOUT5.

Add:
    PARAMETER C_CLKOUT5_FREQ = 125000000
    PARAMETER C_CLKOUT5_PHASE = 0
    PARAMETER C_CLKOUT5_GROUP = NONE
    PARAMETER C_CLKOUT5_BUF = TRUE
    PORT CLKOUT5 = clk_125mhz
   
3) In UCF file

Remove:
   
    Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<3> LOC=AN31  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<2> LOC=AR32  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<1> LOC=AP32  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<0> LOC=AR33  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_TX_EN_0_pin LOC=AP31  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_TX_ER_0_pin LOC=AT31  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<3> LOC=AM33  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<2> LOC=AK33  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<1> LOC=AJ33  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<0> LOC=AJ32  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RX_DV_0_pin LOC=AN33  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RX_ER_0_pin LOC=AP33  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RX_CLK_0_pin LOC=J17  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin LOC=M26  |  IOSTANDARD = LVCMOS25;

Add:

    Net Hard_Ethernet_MAC_RGMII_TXD_0_pin<3> LOC = AN31 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
    Net Hard_Ethernet_MAC_RGMII_TXD_0_pin<2> LOC = AR32 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
    Net Hard_Ethernet_MAC_RGMII_TXD_0_pin<1> LOC = AP32 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
    Net Hard_Ethernet_MAC_RGMII_TXD_0_pin<0> LOC = AR33 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
    Net Hard_Ethernet_MAC_RGMII_TX_CTL_0_pin  LOC = AP31 |  IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
    Net Hard_Ethernet_MAC_RGMII_TXC_0_pin LOC = AM31 | IOSTANDARD =LVCMOS25 | SLEW = FAST | DRIVE = 6;
    Net Hard_Ethernet_MAC_RGMII_RXD_0_pin<3> LOC = AM33 | IOSTANDARD=LVCMOS25;
    Net Hard_Ethernet_MAC_RGMII_RXD_0_pin<2> LOC = AK33 | IOSTANDARD=LVCMOS25;
    Net Hard_Ethernet_MAC_RGMII_RXD_0_pin<1> LOC = AJ33 | IOSTANDARD=LVCMOS25;
    Net Hard_Ethernet_MAC_RGMII_RXD_0_pin<0> LOC = AJ32 | IOSTANDARD=LVCMOS25;
    Net Hard_Ethernet_MAC_RGMII_RX_CTL_0_pin  LOC = AN33 |  IOSTANDARD=LVCMOS25;
    Net Hard_Ethernet_MAC_RGMII_RXC_0_pin LOC=J17 | IOSTANDARD=LVCMOS25; 
   
Remove:
   
    ###### Hard_Ethernet_MAC
    NET "*Hard_Ethernet_MAC/LlinkTemac0_CLK*"           TNM_NET = "LLCLK0"; #name of signal connected to TEMAC LlinkTemac0_CLK input
    NET "*Hard_Ethernet_MAC/SPLB_Clk*"                  TNM_NET = "PLBCLK"; #name of signal connected to TEMAC SPLB_Clk input

    # EMAC0 TX Client Clock
    NET "*Hard_Ethernet_MAC/TxClientClk_0"              TNM_NET = "clk_client_tx0";
    TIMEGRP  "mii_client_clk_tx0"      = "clk_client_tx0";
    TIMESPEC "TS_mii_client_clk_tx0"   = PERIOD "mii_client_clk_tx0" 7500 ps HIGH 50 %;

    # EMAC0 RX Client Clock
    NET "*Hard_Ethernet_MAC/RxClientClk_0"              TNM_NET = "clk_client_rx0";
    TIMEGRP  "mii_client_clk_rx0"      = "clk_client_rx0";
    TIMESPEC "TS_gmii_client_clk_rx0"  = PERIOD "gmii_client_clk_rx0" 7500 ps HIGH 50 %;

    # EMAC0 RX PHY Clock
    NET "*Hard_Ethernet_MAC/MII_RX_CLK_0*"              TNM_NET = "phy_clk_rx0";
    TIMEGRP  "mii_clk_phy_rx0"         = "phy_clk_rx0";
    TIMESPEC "TS_mii_clk_phy_rx0"      = PERIOD "mii_clk_phy_rx0" 40000 ps HIGH 50 %;

    # EMAC0 TX MII 10/100 PHY Clock
    NET "*Hard_Ethernet_MAC/MII_TX_CLK_0*" TNM_NET       = "clk_mii_tx_clk0";
    TIMESPEC "TS_mii_tx_clk0"          = PERIOD "clk_mii_tx_clk0" 40000 ps HIGH 50 %;

    # MII Receiver Constraints:  place flip-flops in IOB
    INST "*mii0*RXD_TO_MAC*"    IOB = TRUE;
    INST "*mii0*RX_DV_TO_MAC"   IOB = TRUE;
    INST "*mii0*RX_ER_TO_MAC"   IOB = TRUE;

    # PHY spec: 10ns setup time, 10ns hold time                            
    # Assumes equal length board traces

    NET "fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin(?)"  TNM = "mii_rx_0";
    NET "fpga_0_Hard_Ethernet_MAC_MII_RX_DV_0_pin"   TNM = "mii_rx_0";
    NET "fpga_0_Hard_Ethernet_MAC_MII_RX_ER_0_pin"   TNM = "mii_rx_0";

    TIMEGRP "mii_rx_0" OFFSET = IN 10 ns VALID 20 ns BEFORE "fpga_0_Hard_Ethernet_MAC_MII_RX_CLK_0_pin";

    # MII Transmiter Constraints:  place flip-flops in IOB
    INST "*mii0*MII_TXD_?"      IOB = TRUE;
    INST "*mii0*MII_TX_EN"      IOB = TRUE;
    INST "*mii0*MII_TX_ER"      IOB = TRUE;

    TIMESPEC TS_PLB_2_TXPHY0 = FROM PLBCLK      TO clk_phy_tx0 40000 ps DATAPATHONLY; #constant value based on Ethernet clock
    TIMESPEC TS_RXPHY0_2_PLB = FROM phy_clk_rx0 TO PLBCLK      10000 ps DATAPATHONLY; #varies based on period of PLB clock

    TIMESPEC "TS_LL_CLK0_2_RX_CLIENT_CLK0"  = FROM LLCLK0 TO clk_client_rx0  8000 ps DATAPATHONLY; #constant value based on Ethernet clock
    TIMESPEC "TS_LL_CLK0_2_TX_CLIENT_CLK0"  = FROM LLCLK0 TO clk_client_tx0  8000 ps DATAPATHONLY; #constant value based on Ethernet clock
    TIMESPEC "TS_RX_CLIENT_CLK0_2_LL_CLK0"  = FROM clk_client_rx0 TO LLCLK0 10000 ps DATAPATHONLY; #varies based on period of LocalLink clock
    TIMESPEC "TS_TX_CLIENT_CLK0_2_LL_CLK0"  = FROM clk_client_tx0 TO LLCLK0 10000 ps DATAPATHONLY; #varies based on period of LocalLink clock

    net "*/hrst*" TIG;

Add:

    ###### Hard_Ethernet_MAC

    # EMAC0 TX Client Clock
    NET "*/RGMII_TX_CTL_0*" TNM_NET = "clk_client_tx0";
    TIMEGRP "rgmii_client_clk_tx0" = "clk_client_tx0";
    TIMESPEC "TS_rgmii_client_clk_tx0" = PERIOD "rgmii_client_clk_tx0" 7800 ps HIGH 50 %;

    # EMAC0 RX Client Clock
    NET "*/RGMII_RX_CTL_0*" TNM_NET = "clk_client_rx0";
    TIMEGRP "rgmii_client_clk_rx0" = "clk_client_rx0";
    TIMESPEC "TS_rgmii_client_clk_rx0" = PERIOD "rgmii_client_clk_rx0" 7800 ps HIGH 50 %;

    # EMAC0 TX PHY Clock
    NET "*/RGMII_TXC_0*" TNM_NET = "clk_phy_tx0";
    TIMEGRP "rgmii_phy_clk_tx0" = "clk_phy_tx0";
    TIMESPEC "TS_rgmii_phy_clk_tx0" = PERIOD "rgmii_phy_clk_tx0" 7800 ps HIGH 50 %;

    # EMAC0 RX PHY Clock
    NET "*/RGMII_RXC_0" TNM_NET = "clk_phy_rx0";
    TIMEGRP "rgmii_clk_phy_rx0" = "clk_phy_rx0";
    TIMESPEC "TS_rgmii_clk_phy_rx0" = PERIOD "rgmii_clk_phy_rx0" 7800 ps HIGH 50 %;

    # Set the IDELAY values on the data inputs.
    # Please modify to suit your design.
    INST "*rgmii0?rgmii_rx_ctl_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii0?rgmii_rx_d0_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii0?rgmii_rx_d1_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii0?rgmii_rx_d2_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii0?rgmii_rx_d3_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii_rxc0_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii0?rgmii_rx_ctl_delay" IDELAY_VALUE = 25;
    INST "*rgmii0?rgmii_rx_d0_delay" IDELAY_VALUE = 25;
    INST "*rgmii0?rgmii_rx_d1_delay" IDELAY_VALUE = 25;
    INST "*rgmii0?rgmii_rx_d2_delay" IDELAY_VALUE = 25;
    INST "*rgmii0?rgmii_rx_d3_delay" IDELAY_VALUE = 25;
    INST "*rgmii_rxc0_delay" IDELAY_VALUE = 0;
    NET "*/LlinkTemac0_CLK*" TNM_NET = "LLCLK";
    TIMESPEC "TS_LL_CLK0_2_RX_CLIENT_CLK0" = FROM LLCLK0 TO clk_client_rx0 8000 ps DATAPATHONLY;
    TIMESPEC "TS_LL_CLK0_2_TX_CLIENT_CLK0" = FROM LLCLK0 TO clk_client_tx0 8000 ps DATAPATHONLY;
    TIMESPEC "TS_RX_CLIENT_CLK0_2_LL_CLK0" = FROM clk_client_rx0 TO LLCLK0 8000 ps DATAPATHONLY;
    TIMESPEC "TS_TX_CLIENT_CLK0_2_LL_CLK0" = FROM clk_client_tx0 TO LLCLK0 8000 ps DATAPATHONLY;
   
4) Change the jumper pins on the board to pins 1/2 for J50 and J49.  There should not be a jumper over J28

4 Replies
8,603 Views
Registered: ‎09-29-2009

Re: Help implementing RGMII on the ML510

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Finally figured it out...

 

 

Converting from MII to RGMII v2.0 for the Virtex-5 ML510

 

1) Configure HARD_ETHERNET_MAC IP

C_NUM_IDELAYCTRL=1
C_IDELAYCTRL_LOC=NOT_SET
Physical Interface Type = RGMII V2.0

2) Modify the MHS file

Remove all MII* from external ports

Add:
    PORT Hard_Ethernet_MAC_RGMII_TXD_0_pin = Hard_Ethernet_MAC_RGMII_TXD_0, DIR = O, VEC = [3:0]
    PORT Hard_Ethernet_MAC_RGMII_TXC_0_pin = Hard_Ethernet_MAC_RGMII_TXC_0, DIR = O
    PORT Hard_Ethernet_MAC_RGMII_TX_CTL_0_pin = Hard_Ethernet_MAC_RGMII_TX_CTL_0, DIR = O
    PORT Hard_Ethernet_MAC_RGMII_RXD_0_pin = Hard_Ethernet_MAC_RGMII_RXD_0, DIR = I, VEC = [3:0]
    PORT Hard_Ethernet_MAC_RGMII_RX_CTL_0_pin = Hard_Ethernet_MAC_RGMII_RX_CTL_0, DIR = I
    PORT Hard_Ethernet_MAC_RGMII_RXC_0_pin = Hard_Ethernet_MAC_RGMII_RXC_0, DIR = I
   
In the xps_ll_temac section of the MHS file, the PORT REFCLK must be connected to a 200MHz clock.  The name may be different between designs.

Add:
    PORT GTX_CLK_0 = clk_125mhz
    PORT REFCLK = clk_200_0000MHzPLL0
    PORT RGMII_RXD_0 = Hard_Ethernet_MAC_RGMII_RXD_0
    PORT RGMII_RX_CTL_0 = Hard_Ethernet_MAC_RGMII_RX_CTL_0
    PORT RGMII_RXC_0 = Hard_Ethernet_MAC_RGMII_RXC_0
    PORT RGMII_TXC_0 = Hard_Ethernet_MAC_RGMII_TXC_0
    PORT RGMII_TX_CTL_0 = Hard_Ethernet_MAC_RGMII_TX_CTL_0
    PORT RGMII_TXD_0 = Hard_Ethernet_MAC_RGMII_TXD_0
   
In the clock_generator section, a 125MHz clock must be added.  The number of the clock depends on the number of other clocks in your design.  Since four clocks already existed, the new one is C_CLKOUT5.

Add:
    PARAMETER C_CLKOUT5_FREQ = 125000000
    PARAMETER C_CLKOUT5_PHASE = 0
    PARAMETER C_CLKOUT5_GROUP = NONE
    PARAMETER C_CLKOUT5_BUF = TRUE
    PORT CLKOUT5 = clk_125mhz
   
3) In UCF file

Remove:
   
    Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<3> LOC=AN31  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<2> LOC=AR32  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<1> LOC=AP32  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_TXD_0_pin<0> LOC=AR33  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_TX_EN_0_pin LOC=AP31  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_TX_ER_0_pin LOC=AT31  |  IOSTANDARD = LVCMOS25  |  SLEW = FAST  |  DRIVE = 6;
    Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<3> LOC=AM33  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<2> LOC=AK33  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<1> LOC=AJ33  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin<0> LOC=AJ32  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RX_DV_0_pin LOC=AN33  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RX_ER_0_pin LOC=AP33  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_RX_CLK_0_pin LOC=J17  |  IOSTANDARD = LVCMOS25;
    Net fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin LOC=M26  |  IOSTANDARD = LVCMOS25;

Add:

    Net Hard_Ethernet_MAC_RGMII_TXD_0_pin<3> LOC = AN31 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
    Net Hard_Ethernet_MAC_RGMII_TXD_0_pin<2> LOC = AR32 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
    Net Hard_Ethernet_MAC_RGMII_TXD_0_pin<1> LOC = AP32 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
    Net Hard_Ethernet_MAC_RGMII_TXD_0_pin<0> LOC = AR33 | IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
    Net Hard_Ethernet_MAC_RGMII_TX_CTL_0_pin  LOC = AP31 |  IOSTANDARD=LVCMOS25 | SLEW=FAST | DRIVE = 24;
    Net Hard_Ethernet_MAC_RGMII_TXC_0_pin LOC = AM31 | IOSTANDARD =LVCMOS25 | SLEW = FAST | DRIVE = 6;
    Net Hard_Ethernet_MAC_RGMII_RXD_0_pin<3> LOC = AM33 | IOSTANDARD=LVCMOS25;
    Net Hard_Ethernet_MAC_RGMII_RXD_0_pin<2> LOC = AK33 | IOSTANDARD=LVCMOS25;
    Net Hard_Ethernet_MAC_RGMII_RXD_0_pin<1> LOC = AJ33 | IOSTANDARD=LVCMOS25;
    Net Hard_Ethernet_MAC_RGMII_RXD_0_pin<0> LOC = AJ32 | IOSTANDARD=LVCMOS25;
    Net Hard_Ethernet_MAC_RGMII_RX_CTL_0_pin  LOC = AN33 |  IOSTANDARD=LVCMOS25;
    Net Hard_Ethernet_MAC_RGMII_RXC_0_pin LOC=J17 | IOSTANDARD=LVCMOS25; 
   
Remove:
   
    ###### Hard_Ethernet_MAC
    NET "*Hard_Ethernet_MAC/LlinkTemac0_CLK*"           TNM_NET = "LLCLK0"; #name of signal connected to TEMAC LlinkTemac0_CLK input
    NET "*Hard_Ethernet_MAC/SPLB_Clk*"                  TNM_NET = "PLBCLK"; #name of signal connected to TEMAC SPLB_Clk input

    # EMAC0 TX Client Clock
    NET "*Hard_Ethernet_MAC/TxClientClk_0"              TNM_NET = "clk_client_tx0";
    TIMEGRP  "mii_client_clk_tx0"      = "clk_client_tx0";
    TIMESPEC "TS_mii_client_clk_tx0"   = PERIOD "mii_client_clk_tx0" 7500 ps HIGH 50 %;

    # EMAC0 RX Client Clock
    NET "*Hard_Ethernet_MAC/RxClientClk_0"              TNM_NET = "clk_client_rx0";
    TIMEGRP  "mii_client_clk_rx0"      = "clk_client_rx0";
    TIMESPEC "TS_gmii_client_clk_rx0"  = PERIOD "gmii_client_clk_rx0" 7500 ps HIGH 50 %;

    # EMAC0 RX PHY Clock
    NET "*Hard_Ethernet_MAC/MII_RX_CLK_0*"              TNM_NET = "phy_clk_rx0";
    TIMEGRP  "mii_clk_phy_rx0"         = "phy_clk_rx0";
    TIMESPEC "TS_mii_clk_phy_rx0"      = PERIOD "mii_clk_phy_rx0" 40000 ps HIGH 50 %;

    # EMAC0 TX MII 10/100 PHY Clock
    NET "*Hard_Ethernet_MAC/MII_TX_CLK_0*" TNM_NET       = "clk_mii_tx_clk0";
    TIMESPEC "TS_mii_tx_clk0"          = PERIOD "clk_mii_tx_clk0" 40000 ps HIGH 50 %;

    # MII Receiver Constraints:  place flip-flops in IOB
    INST "*mii0*RXD_TO_MAC*"    IOB = TRUE;
    INST "*mii0*RX_DV_TO_MAC"   IOB = TRUE;
    INST "*mii0*RX_ER_TO_MAC"   IOB = TRUE;

    # PHY spec: 10ns setup time, 10ns hold time                            
    # Assumes equal length board traces

    NET "fpga_0_Hard_Ethernet_MAC_MII_RXD_0_pin(?)"  TNM = "mii_rx_0";
    NET "fpga_0_Hard_Ethernet_MAC_MII_RX_DV_0_pin"   TNM = "mii_rx_0";
    NET "fpga_0_Hard_Ethernet_MAC_MII_RX_ER_0_pin"   TNM = "mii_rx_0";

    TIMEGRP "mii_rx_0" OFFSET = IN 10 ns VALID 20 ns BEFORE "fpga_0_Hard_Ethernet_MAC_MII_RX_CLK_0_pin";

    # MII Transmiter Constraints:  place flip-flops in IOB
    INST "*mii0*MII_TXD_?"      IOB = TRUE;
    INST "*mii0*MII_TX_EN"      IOB = TRUE;
    INST "*mii0*MII_TX_ER"      IOB = TRUE;

    TIMESPEC TS_PLB_2_TXPHY0 = FROM PLBCLK      TO clk_phy_tx0 40000 ps DATAPATHONLY; #constant value based on Ethernet clock
    TIMESPEC TS_RXPHY0_2_PLB = FROM phy_clk_rx0 TO PLBCLK      10000 ps DATAPATHONLY; #varies based on period of PLB clock

    TIMESPEC "TS_LL_CLK0_2_RX_CLIENT_CLK0"  = FROM LLCLK0 TO clk_client_rx0  8000 ps DATAPATHONLY; #constant value based on Ethernet clock
    TIMESPEC "TS_LL_CLK0_2_TX_CLIENT_CLK0"  = FROM LLCLK0 TO clk_client_tx0  8000 ps DATAPATHONLY; #constant value based on Ethernet clock
    TIMESPEC "TS_RX_CLIENT_CLK0_2_LL_CLK0"  = FROM clk_client_rx0 TO LLCLK0 10000 ps DATAPATHONLY; #varies based on period of LocalLink clock
    TIMESPEC "TS_TX_CLIENT_CLK0_2_LL_CLK0"  = FROM clk_client_tx0 TO LLCLK0 10000 ps DATAPATHONLY; #varies based on period of LocalLink clock

    net "*/hrst*" TIG;

Add:

    ###### Hard_Ethernet_MAC

    # EMAC0 TX Client Clock
    NET "*/RGMII_TX_CTL_0*" TNM_NET = "clk_client_tx0";
    TIMEGRP "rgmii_client_clk_tx0" = "clk_client_tx0";
    TIMESPEC "TS_rgmii_client_clk_tx0" = PERIOD "rgmii_client_clk_tx0" 7800 ps HIGH 50 %;

    # EMAC0 RX Client Clock
    NET "*/RGMII_RX_CTL_0*" TNM_NET = "clk_client_rx0";
    TIMEGRP "rgmii_client_clk_rx0" = "clk_client_rx0";
    TIMESPEC "TS_rgmii_client_clk_rx0" = PERIOD "rgmii_client_clk_rx0" 7800 ps HIGH 50 %;

    # EMAC0 TX PHY Clock
    NET "*/RGMII_TXC_0*" TNM_NET = "clk_phy_tx0";
    TIMEGRP "rgmii_phy_clk_tx0" = "clk_phy_tx0";
    TIMESPEC "TS_rgmii_phy_clk_tx0" = PERIOD "rgmii_phy_clk_tx0" 7800 ps HIGH 50 %;

    # EMAC0 RX PHY Clock
    NET "*/RGMII_RXC_0" TNM_NET = "clk_phy_rx0";
    TIMEGRP "rgmii_clk_phy_rx0" = "clk_phy_rx0";
    TIMESPEC "TS_rgmii_clk_phy_rx0" = PERIOD "rgmii_clk_phy_rx0" 7800 ps HIGH 50 %;

    # Set the IDELAY values on the data inputs.
    # Please modify to suit your design.
    INST "*rgmii0?rgmii_rx_ctl_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii0?rgmii_rx_d0_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii0?rgmii_rx_d1_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii0?rgmii_rx_d2_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii0?rgmii_rx_d3_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii_rxc0_delay" IOBDELAY_TYPE = FIXED;
    INST "*rgmii0?rgmii_rx_ctl_delay" IDELAY_VALUE = 25;
    INST "*rgmii0?rgmii_rx_d0_delay" IDELAY_VALUE = 25;
    INST "*rgmii0?rgmii_rx_d1_delay" IDELAY_VALUE = 25;
    INST "*rgmii0?rgmii_rx_d2_delay" IDELAY_VALUE = 25;
    INST "*rgmii0?rgmii_rx_d3_delay" IDELAY_VALUE = 25;
    INST "*rgmii_rxc0_delay" IDELAY_VALUE = 0;
    NET "*/LlinkTemac0_CLK*" TNM_NET = "LLCLK";
    TIMESPEC "TS_LL_CLK0_2_RX_CLIENT_CLK0" = FROM LLCLK0 TO clk_client_rx0 8000 ps DATAPATHONLY;
    TIMESPEC "TS_LL_CLK0_2_TX_CLIENT_CLK0" = FROM LLCLK0 TO clk_client_tx0 8000 ps DATAPATHONLY;
    TIMESPEC "TS_RX_CLIENT_CLK0_2_LL_CLK0" = FROM clk_client_rx0 TO LLCLK0 8000 ps DATAPATHONLY;
    TIMESPEC "TS_TX_CLIENT_CLK0_2_LL_CLK0" = FROM clk_client_tx0 TO LLCLK0 8000 ps DATAPATHONLY;
   
4) Change the jumper pins on the board to pins 1/2 for J50 and J49.  There should not be a jumper over J28

Observer coldwarcomms
Observer
7,603 Views
Registered: ‎01-16-2010

Re: Help implementing RGMII on the ML510

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Hello,

 

I am working with a ML510 board and followed your instructions, however I ran into some issues. When I tried to generate the system bitstream, I got placement errors saying there were too many IDELAY instantiations. I made a few modifications to the LLTEMAC as outlined below:

 

C_NUM_IDELAYCTRL = 2

C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y6-IDELAYCTRL_X0Y1

 

This passed placement and a bitstream was generated. I am using the Xilinx linux tree and compiled the kernel with RGMII support in LLTEMAC. I set the appropriate jumpers on the ML510 for RGMII. The ML510 is connected to a gigabit switch, however, when I boot the system, I get the following messages:

 

 Configuring network interfaces... eth0: XLlTemac: Options: 0x3fa
eth0: XLlTemac: allocating interrupt 20 for dma mode tx.
eth0: XLlTemac: allocating interrupt 19 for dma mode rx.
eth0: XLlTemac: Not able to set the speed to 1000 (status: 0x7949)
eth0: XLlTemac: We renegotiated the speed to: 100
eth0: XLlTemac: speed set to 100Mb/s
eth0: XLlTemac: Send Threshold = 24, Receive Threshold = 4
eth0: XLlTemac: Send Wait bound = 254, Receive Wait bound = 254

 

It cannot connect at 1000 Mbps. I was just wondering if you could provide any insight as to why this might happen. Was it wrong to make the change I did to the TEMAC. Is there another way to get rid of those placement errors? Would that make the TEMAC behave as shown?

 

Thank you,

 

-Nick

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7,600 Views
Registered: ‎09-29-2009

Re: Help implementing RGMII on the ML510

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Hi Nick,

 

I never had any luck setting the values below that you did:

 

C_NUM_IDELAYCTRL = 2

C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y6-IDELAYCTRL_X0Y1

 

There is a program, ADEPT (or ADAPT, can't remember, there are some posts about it in the forums), that can be used to figure out where the pins are exactly in the FPGA fabric for the C_IDELAYCTRL_LOC variables.  Looks like you chose the right ones if it generated a bitstream.

 

 

Some random networking thoughts:

 

1) Ensure you are using a CAT-5E or CAT-6 network cable.  It should state it on the actual cable.  CAT-5 is capped at 100 Mbps.

2) Ensure the interface on the switch is set to 1000 Mbps.  If it's a Cisco switch, it will usually autonegotiate with the board.  You may have to go in and configure it manually.  Consult the switch manual to do that.  You could also connect it to a computer and see what speed it negotiates.  You can tweak the speed and duplex (of the computer NIC) easily in Windows.

3) Ensure you have the network cable inserted in the correct interface on the board. On my board, the top jack is for MII/RGMII/SGMII and the bottom jack is only SGMII.  It should say something like "ETH(0) Top" printed on the board.

4) Double check the jumpers.

5) Double check the lights on the board to see what your duplex and speed settings are.  There are some LEDs kind of near the ethernet jacks that light up.

 

Hope that helps...

 

Brennon

 

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Observer coldwarcomms
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Registered: ‎01-16-2010

Re: Help implementing RGMII on the ML510

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I got it working. It turned out to be the driver configuration. Selecting the GMII option seems counter intuitive considering there is the MARVELL 88E1111 using RGMII option. However, the RGMII option does not work correctly. Using that driver configuration, negotiation always fell back to 100Mbps or 10Mbps. So, the GMII option is the one you want for the driver to work correctly and negotiate at 1000Mbps. I was using the kernel at http://git.xilinx.com (commit 17431547113100a3ae0a622b9f76ad17fb76eb56).

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