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Observer jchou.1992
Observer
519 Views
Registered: ‎01-01-2019

How can Ultrascal+100G Ethernet IP connect to AXI bus?

Hello:

 

 I'm using ZU17EG for my design. I used Vivado Block Gen to generate "Zynq" and" Ultrascale+100G Ethernet subsystem" in my design.

Then I run "Block & Connection Automation",  only rest & clock signals are connected. All data & control signals are floating. Not interconnection to Zynq. How can I connect them?  Which IP should I add?

 

BTW, Does Xilinx have reference design such as document, schematics, demo program regarding this?

 

Thanks

Jimmy 

 

 

 

 

 

 

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2 Replies
Moderator
Moderator
392 Views
Registered: ‎11-09-2017

Re: How can Ultrascal+100G Ethernet IP connect to AXI bus?

Hi @jchou.1992

Ultrascal+100G Ethernet IP interface is LBUS interface not axi interface.

 

Regards
Pratap

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Participant johnmaclellan
Participant
370 Views
Registered: ‎11-30-2017

Re: How can Ultrascal+100G Ethernet IP connect to AXI bus?

Is there any code or ref design for interfacing the 100G lbus to AXIS?  Thx

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