03-25-2021 06:27 PM
Currently, I am researching the SFP module on ARTIX 7 board but the problem is as follows:
First, I used the GIG_Ethernet PCS / PMA core in the IP Catalog to SGMII mode to loopback 1 SFP module successfully. However, I need to use 2 GIG_Ethernet PCS / PMA cores for 2 SFP ports, there is only 1 GTPE2_COMMON cell. So I create one IP core with the 'Shared Logic within the core' and the other with 'Shared logic in example design'. The IP core with the 'Shared Logic within the core' provided port signals to connect the cores to share the COMMON block ( PLL0OUTCLK_OUT, PLL0OUTREFCLK_OUT, PLL0LOCK_OUT, PLL0REFCLKLOST_OUT, PLL1OUTCLK_OUT, PLL1OUTREFCLK_OUT, userclk, userclk2, gtrefclk_bufg, gtrefclk, rxuserclk, rxuserclk2, mmcm_locked). But IP core with the 'Shared logic in example design' operated incorrectly. I used to debug core to see the gmii_rxd, gmii_rx_dv, gmii_rx_er signals, and no data or pulse on it.
The second problem I want to ask the debug PLL solution (the COMMON block). Can you help me?
Hope you support!
03-26-2021 03:28 AM
Hi @Dat ,
Can you please check this thread first and see if it helps? You can compare the connections in this BD with yours:
The above thread works well but seems to have delayed resetdone issue. When you say the 2nd PCS/PMA core is not operating correctly, what does this mean? Please provide more details on it.
03-26-2021 09:22 AM
Thank you for your response. I've read the idea you mentioned but I think it is correct. In my system summary, SFP2 was created one IP core with the 'Shared Logic within the core' and SFP1 was created the other with 'Shared logic in example design'. SFP2 provided port signals to connect SFP1 to share the COMMON block ( PLL0OUTCLK_OUT, PLL0OUTREFCLK_OUT, PLL0LOCK_OUT, PLL0REFCLKLOST_OUT, PLL1OUTCLK_OUT, PLL1OUTREFCLK_OUT, userclk, userclk2, gtrefclk_bufg, gtrefclk, rxuserclk, rxuserclk2, mmcm_locked).
Look at pictures, you can see when I loopback SFP1 and SFP2, no data in SFP2 's RXD and not enough data in SFP1's RXD. I don't know Why those errors. Can you help me?
Thank you very much!
03-26-2021 09:47 AM
Hi @Dat ,
Can you please explain your setup and the data path? What do you mean by looping back SFP1 and SFP2? Does SFP1 TX go to SFP2 RX? Or is the internet loopback on each SFPs respectively?
Do you have Wireshark open and see if the data is coming in at the RX path?
03-26-2021 09:24 PM
Thank you for replying, I setup SFP1 TX go to SFP2 RX and SFP2 Tx go to SFP1 RX. Here, SFP2 shares the COMMON block for SFP1. The result is no data in SFP2 's RX and not enough data in SFP1's RX.
Also, I used the module to convert SFP to Ethernet to test with Wireshark but no data was received by me. I think it is because of the incorrect configuration. Look at the pictures, It is SFP1 's configuration and SFP2 's configuration.
Can you help me explain two problems?
Thank you very much!
03-29-2021 01:23 AM
HI @Dat ,
When you say SFP1/2, do you have SFP modules physically connection on the boards' SFP ports? And you have a loopback cable connected between them?
Or the SFP1 and SFP2 which in your BD above only means the PCS/PMA cores which are connected with one's txd to the other ones' rxd? This is very important to understand.
If you mean the two IPs connected back to back, you can run the simulation to figure out what might cause the issue.
if you are using SFP modules and loopback cables, I'd first check if one port is able to communicate with a PC first.
I am not sure I understand "Also, I used the module to convert SFP to Ethernet to test with Wireshark but no data was received by me"...if there is no TX data to your link partner, you will need to check if there is the link is actually up. If AN is turned on, maybe try turning it off and see if you could establish a connection.
03-29-2021 08:31 AM
I've SFP modules physically connected on the board's SFP ports and I have a loopback cable connected between them.
I've run the simulation to figure out what might cause the issue but have one error:" [VRFC 10-380] binding entity gig_ethernet_pcs_pma_1_support does not have generic example_simulation ["D:/Vivado_Debug/DEBUG_XILLINX/DEBUG_ARTIX7/gig_ethernet_pcs_pma_1_ex.srcs/sources_1/ip/gig_ethernet_pcs_pma_1/synth/gig_ethernet_pcs_pma_1.vhd":199] " . I mean the core with "Share logic within the core" can't simulate because it default read-only.
03-29-2021 08:36 AM
Hi @Dat ,
Thanks for the setupo details.
If connecting to a end computer without the loopback cable on each of the SFP ports, do you see a linkup on both ports respectively? This is to confirm if each IP and up and running with the SFP port.
03-29-2021 08:52 AM
Hi @nanz ,
I'm sorry but I don't know your solution. I can't connect with the PC because it has no SFP port. I have only connected with Catalyst 2960-X Series switches, but the link led doesn't put on.
03-29-2021 08:58 AM
Hi @Dat ,
It's 1G connection. Do you have an SFP which can connect an ethernet cable so it can be connected to the PC to check? You can open the Wireshark on the PC and see if any packets are captured coming in?
It does sound like the packets are stuck/stalled with the external loopback cable. I am wondering if the cable has been used successfully in other setups?
03-29-2021 09:08 AM
I have tested with the module to convert SFP to Ethernet, I used Wireshark on the PC to capture packets but not any packets. I've tested successfully the method on KCU040 Board. I think the packets can't go through the external loopback cable. How must I do?
03-29-2021 09:30 AM
Hi @Dat ,
There are two things you described:
With SFP to PC, you cannot see any packets either, right? But the SFP to Ethernet is working on KCU040? If this is the case, what are the differences between IPs used on KCU040 and this one? And if any settings in SFP module needs to be looked at?
Are there any settings in the external loopback cable that you need to look at? Have you read the data sheet? Has this cable been used successfully in another setup? What are the differences?