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Explorer
Explorer
701 Views
Registered: ‎12-12-2018

How to assign RGMII pins in zu11eg?

Hi everyone

    what's kind of  port  does the RGMII port can be use in ultrascale+ fpga?

    When I use Tri_mode_ethernet_mac ip with Rgmii in zu11eg, I don't know how to set them.

	output					o_poe_rstn,	
	output  [GE_NUM - 1 	: 0]		o_phy_resetn,
	output 	[GE_NUM*4 - 1 	: 0]  	        o_rgmii_txd,
	output  [GE_NUM - 1 	: 0]          	o_rgmii_tx_ctl,
	output  [GE_NUM - 1 	: 0]          	o_rgmii_txc,
	input  	[GE_NUM*4 - 1 	: 0]		i_rgmii_rxd,
	input  	[GE_NUM - 1 	: 0]          	i_rgmii_rx_ctl,
	input   [GE_NUM - 1 	: 0]          	i_rgmii_rxc,	
	inout   [GE_NUM - 1 	: 0]            io_phy_mdio,
	output  [GE_NUM - 1 	: 0]            o_phy_mdc

Does t/rxc must set DBC port and QBC port?
Does t/rxd must set  normal HP port ?
what 's the relationship between these port ? 
when I set 8 tri_mode_ethernet_mac in my project,I got this result.

err.png

 

what's that mean?

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5 Replies
Scholar
Scholar
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Registered: ‎08-07-2014

@xumoxiao,

you have not pin-mapped your RGMII ports to the FPGA pins.

Refer to the ultrascale data sheet as to which FPGA pins you can connect them. You cannot connect them to any IO port. That is why you are seeing the 1st error message.

------------FPGA enthusiast------------
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Explorer
Explorer
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Registered: ‎12-12-2018

@dpaul24
Thanks for your reply.
Can you describe it in more detail?
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Scholar
Scholar
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Registered: ‎08-07-2014

@xumoxiao,

I might have misunderstood your initial question. It seems you have connected the rgmii ports to the FPGA pins.

Now please re-read the Vivado generated messages. Your *txc now are connected to pins D19 and T15 which cannot be obeyed due to the placement of *_delay_rgmii module/s.

You need to look in to your placed design. Find out the pins suitable to be connected near to the placed *_delay_rgmii module/s and connect the *txc to them.

------------FPGA enthusiast------------
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Explorer
Explorer
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Registered: ‎12-12-2018

@dpaul24.

I think I found the key. In Pg051, I found that.
企业微信截图_15850554558903.png

So the red box in the illustration below cannot be used, only the remaining DBC, QBC, GC pins can be used
1.png

I ca n’t understand the phrase "RX Data/Control pins or any input pin which needs to be routed through IDELAY cannot be placed at BITSLICE below TXC".

Because the pin assignments in the picture below are correct

2.png

But TXC is above RXCTL!!!
How to explain this

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Explorer
Explorer
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Registered: ‎12-12-2018

Please help!
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