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Adventurer
Adventurer
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Registered: ‎06-27-2016

How to handle a packet while calculating CRC

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Hi, 

I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a  <1600Byte  data.

Now shall it extract different package element line them in a long shift register and at same time pass it to a fifo to buffer it and calculate crc32 which will take some clock cycles. Now if CRC calculated matched what received  pass data to nxt stage else rst fifo.

 

 

Is there a better technique for it?

Thank-You in advance.

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Adventurer
Adventurer
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Registered: ‎06-27-2016

Re: How to handle a packet while calculating CRC

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@dpaul24 Actually  it is a  <50Mbps interface with custom Phy .

I was looking for on the fly CRC32 calculation which don't require unnecessary holding of large data packet inside FPGA.

Found a concept of Parallel bit crc using multiple serial LFSR in parallel. Its fast and easy on resource.

View solution in original post

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Scholar
Scholar
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Registered: ‎08-07-2014

Re: How to handle a packet while calculating CRC

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@yogesh_tripathi,

I don't understand your question and what you are trying to do!

 

I'm trying to process a Ethernet type package.

Are you taking about raw Ethernet frames?

 

Suppose if i have detected SFD and now have a  <1600Byte  data.

Indicates you have received/receiving a packet which is yet to be fed into a MAC core.

 

Now shall it extract different package element line them in a long shift register and at same time pass it to a fifo to buffer it and calculate crc32 which will take some clock cycles.

I don't understand this.

Generally a Xilinx MAC core does what you are trying to do. It receives a complete frame, strips off the SFD, calc the FCS against the rx FCS. If a bad frame is received then also the frame is passed to the rx FIFO with an indicator signal. See the Xilinx TEMAC example_design to find out what actually happens at the rx_fifo when a bad frame is received.

 

Anyways the CRC/FCS cannot be compared until the complete frame is received. You have the buffer the frame data until the last FCS byte is rx (if the farme needs to be passed on from the TEMAC to the rx_fifo). In my opinion, constantly calc the FCS value as the bytes are received should be a faster way.

 

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Adventurer
Adventurer
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Registered: ‎06-27-2016

Re: How to handle a packet while calculating CRC

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@dpaul24 Actually  it is a  <50Mbps interface with custom Phy .

I was looking for on the fly CRC32 calculation which don't require unnecessary holding of large data packet inside FPGA.

Found a concept of Parallel bit crc using multiple serial LFSR in parallel. Its fast and easy on resource.

View solution in original post

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