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612 Views
Registered: ‎01-29-2021

How to test the ethernet connection of Xilinx VC707

I am trying to connect the Xilinx VC707 Rev 1.1 to the system via a ethernet cable. Although NIC and the IP Address is configured when the tool tries to ping to the board the connection is not established.

 

How can I check if the ethernet of the board is working correctly and not faulty

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dpaul24
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Registered: ‎08-07-2014

@mayurxilinxanv 

How can I check if the ethernet of the board is working correctly and not faulty

What changes have you done to the implemented FPGA design such that the board can receive external Ethernet data?

A minimum requirement would be to set the Eth PHY registers and set up the Eth MAC core.

https://www.xilinx.com/support/documentation/boards_and_kits/virtex-7/vc707-ethernet-pdf-xtp148-14.3.pdf

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Registered: ‎01-29-2021

Thanks for the immediate response, the ethernet would be used to connect to Matlab which connects to the board via the ethernet .. I am infact not using any ETh PHY/MAC core .. just the port for communication ... 

The the NIC is connected to the board and an IP Address is assigned ... when a ping is been executed .. there is no response .. 

Any idea what would be wrong ? 

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dpaul24
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Registered: ‎08-07-2014

@mayurxilinxanv ,

I do not think you understood my previous response.

I am infact not using any ETh PHY/MAC core .. just the port for communication

If there is no Ethernet system running in the FPGA board, how do you expect get a response for ping from the board? The FPGA board does not have a "power up and play" Ethernet system, you need to build one.

So set up an Eth system in your board, read the PDF link I have posted above.

I would also recommend you to study the OSI model for Ethernet ,Layer1(Eth PHY) and Layer2 (Eth MAC).

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Registered: ‎01-29-2021

oh ok .. thats a nice catch ... I would surely try that for starting .. 

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Registered: ‎01-29-2021

Thanks dpaul24,

Just to confirm this .. 

I setup the basic ethernet requirements on the board using the jtag .. once done .. I again use the Jtag to program another bitstream replicating a different function and use the ethernet to communicate ...  ? 

 

OR should I build a single bitstream which has both the ethernet and the required design and then program the fpga .. ? 

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dpaul24
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Registered: ‎08-07-2014

The 2nd one.

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Registered: ‎01-29-2021

Where can I find the ethernet design files .. the website doesnt seem to have them now 

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dpaul24
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Registered: ‎08-07-2014

@mayurxilinxanv ,

The zip files are in the Answer Record https://www.xilinx.com/support/answers/46384.html

 

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