04-01-2015 12:29 AM
Hi, i have one board with 2 Pal inputs with decoders (ADC).
The second board have a processor that accepts video (interlaced or progressive) for processing.
The boards are connected by transceivers.
My idea was to convert Pal to SDI SD, but on the receiver side i will not have the original recovered clock signal but a clock enable (since Xilinx transceiver can't recover this slow clock).
The processor needs data and clock, i can use the clock enable instead of the clock, this could work but i think it isn't a clean solution.
How should i recover the original clock? Should i use a different standard/method to transfer those videos? (For example deinterlacing at the source and using SDI HD for transfer? Not use SDI at all?)
I'm trying to keep latency as low as possible
04-01-2015 12:35 AM
Check if below XAPP helps for the SD SDI implementation.
04-08-2015 01:56 AM
The problem i'm facing is the conversion from PAL-> SDI SD.
I think that to keep latency low, i'll need to frequency lock the PAL decoder frequency to the SDI SD trasmitter frequency.
I could use the VCXO Replacement Technique http://www.xilinx.com/support/documentation/application_notes/xapp591-triple-rate-sdi-passthrough-vcxo-replacement.pdf
but there isn't an application note for Artix...
i would know if this is the correct way or if there are simpler/better solutions