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Registered: ‎09-16-2020

How to use SFP on ZCU111 ?

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Hello,

 

I'm trying to use SFP connectors on a ZCU111 board, with Zynq support and 10/25G Ethernet Subsystem. I'm using Vivado 2018.3.

It seem that I have a clock problem. What clock I need to use in the IP ?

In the UG1271 (https://www.xilinx.com/support/documentation/boards_and_kits/zcu111/ug1271-zcu111-eval-bd.pdf#G5.593914), I found a SFP_SI5382_CLOCKS that I think think I need to use with this GT connector ?

 

But, Vivado don't propose this clock, so a made a custom port and add a contain file whit this :

set_property PACKAGE_PIN AW13 [get_ports "SFP_REC_CLOCK_C_N"] ;# Bank 64 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_64
set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_N"] ;# Bank 64 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_64
set_property PACKAGE_PIN AW14 [get_ports "SFP_REC_CLOCK_C_P"] ;# Bank 64 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_64
set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_P"] ;# Bank 64 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_64

 

Of course it's not working. Do you know why ?

 

 

 

Finally, I would like to communicate between RFSoC and a 25Gb PCIe card on a PC. 

Moreover, do you have some information about how to make this ?

 

Thank you very much

 

Damien

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Registered: ‎09-16-2020

Hello,

 

Indeed, it was a little mistake on the XDC file !

With the help of https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet, the correct XDC file for ZCU111 and the USER_MGT_SI570 clock is the following :

set_property PACKAGE_PIN V31 [get_ports gt_ref_clk_clk_p]
#create_clock -period 6.400 -name gt_ref_clk [get_ports gt_ref_clk_clk_p]

 

Now, I will continue to follow the wiki in order to can use SFP connection with Linux

 

Thank you very much

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Registered: ‎09-12-2007

Have  look at the wiki below. There is a a demo for the ZCU102 that describes the ref clock (156.25Mhz)

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/478937213/MPSoC+PS+and+PL+Ethernet+Example+Projects

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Registered: ‎09-16-2020

Thank you for your answers!

 

But, this is normal that Vivado don't want to generate bitstream and make this error :

 

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 9 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sfp_clk_clk_n, and sfp_clk_clk_p.

Of course sfp_clk is the name of the custom port that I make and add in XDC file

 

Thank you

 

Damien

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Registered: ‎09-12-2007

looks like the XDC is incorrect. You can open the implemented design, and do this in the io planner GUI to make sure that that you are not making errors here

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Registered: ‎09-16-2020

Hello,

 

Indeed, it was a little mistake on the XDC file !

With the help of https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet, the correct XDC file for ZCU111 and the USER_MGT_SI570 clock is the following :

set_property PACKAGE_PIN V31 [get_ports gt_ref_clk_clk_p]
#create_clock -period 6.400 -name gt_ref_clk [get_ports gt_ref_clk_clk_p]

 

Now, I will continue to follow the wiki in order to can use SFP connection with Linux

 

Thank you very much

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