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Registered: ‎07-17-2014

I2C master/Slave controller core as per Xilinx XAPP385 & XAPP333

Dear Sir,


We are trying to implement the I2C master/Slave controller core as per Xilinx XAPP385 . We have downloaded the the core xapp333 from Xilinx Website.


We have integrated this code to FPGA and were able to interface (Write/Read) from microprocessor (Freescale MPC8360) with few modifications for uC interface.


Now we are facing the problem, when we configure this core as Master and using an external Slave ( 3rd Party tool - Total Phase USB AARDVARK - as I2C Slave).


Also we have checked the same with one more board as I2C Slave which is tested succesfully separately, and the result is same.


We have written the intialization & master bringup code into MPC8360 U-Boot code- (Attached the same)


We observed that this core is able to generate the SCL, SDA,  START condition, slave address as per I2C Protocol, but the  slave is not responding with the ACK bit .


What could be the problem for Slave not acknowledging with ACK bit ? Please find the attached waveforms for the same.


We have changed the following in XAPP 333 - VHDL code :


1) System clock changed from 2 MHz to 8 MHz and changed the different constants accordingly- (Attached the same)

2) Modified the registers addresses as per our board address map.


Kindly give your suggestions for resolving this issue.








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