09-10-2014 07:37 AM
I was trying to generate an IBERT GTX core (v2.06.a) for a custom board with a Virtex6 using ISE DS/Core Generator v14.7. The board has a 127 MHz clock that I try to use as a system clock. The core generation fails during map because it creates an MMCM in order to scale down the system clock to 100 MHz but the PLL VCO frequency turns out to be 127*25/2=1587.5 MHz which is apparently outside the allowed range of 600-1440 MHz according to the error message.
I was able to get around this problem by disabling the bitstream generation during the core creation and then manually modify the MMCM parameters in the UCF file to get a VCO frequency of 1270 MHz and then implement the design, but this is quite cumbersome.
The reason I am writing is because this error seems to be in contradiction with some of the IBERT and Virtex6 documents (and my brief search of forums could not find any post with a similar problem). Specifically, DS732 for IBERT Virtex6 GTX says the system clock is divided down internally using an MMCM if it is running faster than 150 MHz. But even if an MMCM is necessary to do this, the allowed VCO frequency range for a Virtex6 MMCM is 600-1600 MHz according to the Virtex-6 characteristics in DS150. So a 127 MHz system clock should not cause any problem even with the default MMCM settings in the IBERT design.
09-10-2014 10:30 PM
09-11-2014 07:29 AM
Thank you for the reply. I missed ds152. I see, indeed the speed grade of my Virtex 6 is -2, so the 1440 MHz limit for F_VCO seems to be valid.
Now the only question is why the IBERT Virtex6 GTX IP core (v2.0) data sheet (ds732) does not point out to use a system clock slower than F_VCO/12.5 or rather why the core is not generated with a more appropriate MMCM multiplier that would allow a wider range of system clocks as indicated by ds732. In contrast, the IBERT 7-Series GTX core (v2.0) works out of the box even with a 200 MHz system clock.