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Registered: ‎06-26-2014

IP functioning issues after integrating with PS



I have a customized 10G-BASE-R core which functions separately when I implement and program the bitstream on hardware. I use system clock pins (G9 and H9) in the design.


But, when I try to integrate it with Zynq PS IP and provide a clock from clock-configuration-PL clocks (FCLK_CLK0),  then the block fails to function as before. 


When I use only bitstream file it works, when I use a block digaam with PS IP , and then export it to SDK, it fails to synchronize wit the external ADC/DAC boards.


Also, I have separately tested another module where PS connects to LEDs  through an axi interconnect, and exported this project to hardware. Then upon programming the LEDs, that project works correctly as expected.


Integrating both together doesnt work.


What can possible be the issues?


What is the difference betwen SYSCLK_P,SYSCLK_N(H9,G9 pair) and the clock generated from the PS ?


Are there other possible issues with exporting the hardware? If so what are they ?


Can I use elf file from a different sdk to program with current project's bitstream?





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Registered: ‎03-31-2012

First make sure that the clock you generate from ps (fclk_clk0) is actually 200 MHz. If that really checks out, the issue could be the quality of the clock. SYSCLK_P/N comes from a low jitter 200 MHz oscillator but the output of a PLL which multiplies from 33 MHz. Its jitter characteristics might be out of spec for the 10g core.
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Registered: ‎06-26-2014

I tried having these disconnected to see if it works upon providing the beter quality SYSCLK clock, but It did not ,which means jitter isnt the issue here.


Case 1-(Correctly functional):

Block diagram- No 10gcore- Only Zynq,reset,AXI interconnect,AXI GPIO.

This block diagram is need to export hardware to SDK, so that the ARM clock can be programmed to generate the required 312.5 MHz

Top module - 10g core verilog source


Case 2- ( Not functional):

Block diagram- Zynq,reset, AXI interconnect,AXI GPIO-connected , 10g core instance disconnected from these blocks.

Top-module- HDL wrapper of above block diagram.


What is functionally the difference between exporting above cases to SDK, the constraints,etc remain the same.


Is there anything unique about the way the BSP gets generated, why does addign them in the same bd stops them from functioning.


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