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Observer
Observer
1,013 Views
Registered: ‎03-14-2018

Integrated 100G subsystem Rx pause frame processing

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Hello,

I implemented the IP 100G ethernet. Everything works well, but the core doesn't inform me when a pause frame is received.

 

Bit "ctl_rx_forward_control"is set '1'  but  stat_rx_pause_req[8:0] doens't change.

 

What do I miss?

 

Thanks

regards

Dominique

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Observer
Observer
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Registered: ‎03-14-2018
I tested both with a NIC card and a switch (both sent pause frame)
but the IP core doesn't see it

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

Hi,

You will need to make sure ctl_rx_pause_* filter options to match the pause frames that you will be seeing.  If you enable both TX and RX pause logic in the GUI, the example design simulation sends and receives pause frames at the end of the simulation that you can use as an example.

 

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Observer
Observer
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Registered: ‎03-14-2018

Hi,

 

I tested the simulation to compare the packet I receive from the "real world" and the packet simulated.

 

In both 4 words of 128 bit are received. packet structure are the same. (MAC address destination)

In the simulation MAC address source are 0x0  in my case it is the PC MAC address

Others words are the same  x8808 x0001  and the time

 

I will include a switch between the kit and the PC to see if the pause frame send but the switch is seen..

 

 

one question: what do you mean by  "make sure ctrl_rx_pause_* filter options "   ? is it the option when we create the IP (wizard)??

 

thanks

Regards

Dominqiue

 

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Observer
Observer
861 Views
Registered: ‎03-14-2018
I tested both with a NIC card and a switch (both sent pause frame)
but the IP core doesn't see it

View solution in original post

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Observer
Observer
825 Views
Registered: ‎03-14-2018

Hello,

The bit ennable were not set..

 

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