09-04-2018 07:29 AM
I implemented the IP 100G ethernet. Everything works well, but the core doesn't inform me when a pause frame is received.
Bit "ctl_rx_forward_control"is set '1' but stat_rx_pause_req[8:0] doens't change.
What do I miss?
09-07-2018 07:13 AM
You will need to make sure ctl_rx_pause_* filter options to match the pause frames that you will be seeing. If you enable both TX and RX pause logic in the GUI, the example design simulation sends and receives pause frames at the end of the simulation that you can use as an example.
09-12-2018 06:50 AM
I tested the simulation to compare the packet I receive from the "real world" and the packet simulated.
In both 4 words of 128 bit are received. packet structure are the same. (MAC address destination)
In the simulation MAC address source are 0x0 in my case it is the PC MAC address
Others words are the same x8808 x0001 and the time
I will include a switch between the kit and the PC to see if the pause frame send but the switch is seen..
one question: what do you mean by "make sure ctrl_rx_pause_* filter options " ? is it the option when we create the IP (wizard)??