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gaviel
Newbie
Newbie
7,233 Views
Registered: ‎09-11-2014

Inter-FPGA cross Vendor serial comm. - recommendations?

Greetings!

 

We have one "manager" FPGA on our board and several slave FPGA's.

 

Are there any suggestions for a simple, lightweight, serial, low pin count protocol to make this happen?

For us, i2c/spi and such are too slow, but on the other hand we don't really need high bit rates (Gigabits). Something that runs at 500MBit/sec will do just fine.

 

Ability to be cross FPGA vendor (sorry Xilinx! :)) and cross FPGA family is also important.

 

I've found : http://www.streamdsp.com/sfpdp.htm.

 

any other suggestions that might fit? anybody has any experience with the above offering?

 

many thanks in advance,

 

Gal.

 

 

 

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gszakacs
Instructor
Instructor
7,223 Views
Registered: ‎08-14-2007

The last time I used serial FPDP it still required the use of Rocket I/O (MGT, GTP, GTX, GTH ...) rather than standard IO pins.  At 500 Mbps, you could possibly distribute a 250 MHz clock around the board and use standard IOB's with DDR or SERDES functions.  What you lose with standard IOB's is the ability to do clock recovery without oversampling.  So you can't just send 8b/10b encoded data around the board between standard IO pins and expect to get the maximum bit rates published in the data sheets for the SERDES interface.  If you are willing to distribute the bit rate clock, then standard IOB's should be fine up to the data sheet numbers (with some work).

-- Gabor
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